1. 20 10月, 2014 1 次提交
  2. 31 7月, 2014 2 次提交
  3. 02 7月, 2014 2 次提交
  4. 25 6月, 2014 1 次提交
  5. 19 6月, 2014 1 次提交
    • S
      ahci: imx: manage only sata_ref_clk in imx_sata_enable[disable] · e6dd42a9
      Shawn Guo 提交于
      Doing suspend/resume on imx6q and imx53 boards with no SATA disk
      attached will trigger the following warning.
      
      ------------[ cut here ]------------
      WARNING: CPU: 0 PID: 661 at drivers/ata/libahci.c:224 ahci_enable_ahci+0x74/0x8)
      Modules linked in:
      CPU: 0 PID: 661 Comm: sh Tainted: G        W     3.15.0-rc5-next-20140521-000027
      Backtrace:
      [<80011c90>] (dump_backtrace) from [<80011e2c>] (show_stack+0x18/0x1c)
       r6:803a22f4 r5:00000000 r4:00000000 r3:00000000
      [<80011e14>] (show_stack) from [<80661e60>] (dump_stack+0x88/0xa4)
      [<80661dd8>] (dump_stack) from [<80028fdc>] (warn_slowpath_common+0x70/0x94)
       r5:00000009 r4:00000000
      [<80028f6c>] (warn_slowpath_common) from [<80029024>] (warn_slowpath_null+0x24/)
       r8:808f68c4 r7:00000000 r6:00000000 r5:00000000 r4:e0810004
      [<80029000>] (warn_slowpath_null) from [<803a22f4>] (ahci_enable_ahci+0x74/0x80)
      [<803a2280>] (ahci_enable_ahci) from [<803a2324>] (ahci_reset_controller+0x24/0)
       r8:ddcd9410 r7:80351178 r6:ddcd9444 r5:dde8b850 r4:e0810000 r3:ddf35e90
      [<803a2300>] (ahci_reset_controller) from [<803a2c68>] (ahci_platform_resume_ho)
       r7:80351178 r6:ddcd9444 r5:dde8b850 r4:ddcd9410
      [<803a2c30>] (ahci_platform_resume_host) from [<803a38f0>] (imx_ahci_resume+0x2)
       r5:00000000 r4:ddcd9410
      [<803a38c4>] (imx_ahci_resume) from [<803511ac>] (platform_pm_resume+0x34/0x54)
      ....
      
      The reason is that the SATA controller has no working clock at this
      point, and thus ahci_enable_ahci() fails to enable the controller.  In
      case that there is no SATA disk attached, the imx_sata_disable() gets
      called in ahci_imx_error_handler(), and both sata_clk and sata_ref_clk
      will be disabled there.  Because all the imx_sata_enable() calls
      afterward will return immediately due to imxpriv->no_device check, the
      SATA controller working clock sata_clk will never get any chance to be
      enabled again.
      
      This is a regression caused by commit 90870d79 (ahci-imx: Port to
      library-ised ahci_platform).  Before the commit, only sata_ref_clk is
      managed by the driver in enable/disable function.  But after the commit,
      all the clocks are enabled/disabled in a row by ahci platform helpers
      ahci_platform_enable[disable]_clks.  Since ahb_clk is a bus clock which
      does not have gate at all, and i.MX low-power hardware module already
      manages sata_clk across suspend/resume cycle, the only clock that needs
      to be managed by software is sata_ref_clk.
      
      So instead of using ahci_platform_enable[disable]_clks to manage all
      the clocks in a row from imx_sata_enable[disable], we should manage
      only sata_ref_clk in there.
      Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
      Fixes: 90870d79 (ahci-imx: Port to library-ised ahci_platform)
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Acked-by: NHans de Goede <hdegoede@redhat.com>
      e6dd42a9
  6. 20 5月, 2014 1 次提交
  7. 15 5月, 2014 1 次提交
  8. 05 5月, 2014 2 次提交
    • S
      ahci: imx: software workaround for phy reset issue in resume · e783c51c
      Shawn Guo 提交于
      When suspending imx6q systems which have rootfs on SATA, the following
      error will likely be seen in resume.  The SATA link will fail to come
      up, and it results in an unusable system across the suspend/resume
      cycle.
      
      $ echo mem > /sys/power/state
      PM: Syncing filesystems ... done.
      PM: Preparing system for mem sleep
      Freezing user space processes ... (elapsed 0.002 seconds) done.
      Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
      PM: Entering mem sleep
      sd 0:0:0:0: [sda] Synchronizing SCSI cache
      sd 0:0:0:0: [sda] Stopping disk
      PM: suspend of devices complete after 61.914 msecs
      PM: suspend devices took 0.070 seconds
      PM: late suspend of devices complete after 4.906 msecs
      PM: noirq suspend of devices complete after 4.521 msecs
      Disabling non-boot CPUs ...
      CPU1: shutdown
      CPU2: shutdown
      CPU3: shutdown
      Enabling non-boot CPUs ...
      CPU1: Booted secondary processor
      CPU1 is up
      CPU2: Booted secondary processor
      CPU2 is up
      CPU3: Booted secondary processor
      CPU3 is up
      PM: noirq resume of devices complete after 10.486 msecs
      PM: early resume of devices complete after 4.679 msecs
      sd 0:0:0:0: [sda] Starting disk
      PM: resume of devices complete after 22.674 msecs
      PM: resume devices took 0.030 seconds
      PM: Finishing wakeup.
      Restarting tasks ... done.
      $ ata1: SATA link down (SStatus 1 SControl 300)
      ata1: SATA link down (SStatus 1 SControl 300)
      ata1: limiting SATA link speed to 1.5 Gbps
      ata1: SATA link down (SStatus 1 SControl 310)
      ata1.00: disabled
      ata1: exception Emask 0x10 SAct 0x0 SErr 0x4040000 action 0xe frozen t4
      ata1: irq_stat 0x00000040, connection status changed
      ata1: SError: { CommWake DevExch }
      ata1: hard resetting link
      sd 0:0:0:0: rejecting I/O to offline device
      sd 0:0:0:0: killing request
      sd 0:0:0:0: rejecting I/O to offline device
      Aborting journal on device sda2-8.
      sd 0:0:0:0: rejecting I/O to offline device
      EXT4-fs warning (device sda2): ext4_end_bio:317: I/O error writing to inode 132577 (offset 0 size 0 starting block 26235)
      Buffer I/O error on device sda2, logical block 10169
      ...
      
      It's caused by a silicon issue that SATA phy does not get reset by
      controller when coming back from LPM.  The patch adds a software
      workaround for this issue.  It enforces a software reset on SATA phy
      in imx_sata_enable() function, so that we can ensure SATA link will
      come up properly in both power-on and resume.
      
      The software reset is implemented by writing phy reset register through
      the phy control register bus interface.  Functions
      imx_phy_reg_[addressing|write|read]() implement this bus interface, while
      imx_sata_phy_reset() performs the actually reset operation.
      Signed-off-by: NRichard Zhu <r65037@freescale.com>
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      e783c51c
    • S
      ahci: imx: add namespace for register enums · 24a9ad5b
      Shawn Guo 提交于
      Update register enums a little bit to add proper namespace prefix, and
      have the names match i.MX reference manual.
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      24a9ad5b
  9. 07 3月, 2014 1 次提交
  10. 23 2月, 2014 1 次提交
  11. 12 12月, 2013 1 次提交
  12. 03 12月, 2013 4 次提交
  13. 15 10月, 2013 1 次提交
    • R
      ahci: imx: setup power saving methods · 8b789d89
      Richard Zhu 提交于
      In order to save power consumption as much as possible.
      
      * Disable sata phy internal pll reference clock when sysetem enter
        into suspend mode, enable it after resume.
      
      * Setup module parameter used to enable imx ahci test power down
        mode(PDDQ) or not, when there is no device detected on the port
      
      * minor modifications:
        - The format of the copyright is changed, because that the original
          one can't pass fsl internal patch reivew without the character
          '(c)'.
        - Exports ahci_platform_ops and ahci_error_handler().
      
      NOTE:
      * The hot-plug can't be supported when PDDQ mode is ever enabled.
      
      * module parameter usage how-to:
        - default: enable PDDQ mode when no device detected.
        - add "ahci-imx.hotplug=1" into kernel command line if your don't
          want to enable PDDQ mode when no device detected on the port.
      
      tj: Slightly updated description and comments.
      Signed-off-by: NRichard Zhu <r65037@freescale.com>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      8b789d89
  14. 25 7月, 2013 1 次提交
    • R
      ahci_imx: add ahci sata support on imx platforms · 9e54eae2
      Richard Zhu 提交于
      imx6q contains one Synopsys AHCI SATA controller, But it can't share
      ahci_platform driver with other controllers because there are some
      misalignments of the generic AHCI controller - the bits definitions of
      the HBA registers, the Vendor Specific registers, the AHCI PHY clock
      and the AHCI signals adjustment window(GPR13 register).
      
       - CAP_SSS(bit20) of the HOST_CAP is writable, default value is '0',
         should be configured to be '1'
      
       - bit0 (only one AHCI SATA port on imx6q) of the HOST_PORTS_IMPL
         should be set to be '1'.(default 0)
      
       - One Vendor Specific register HOST_TIMER1MS(offset:0xe0) should be
         configured regarding to the frequency of AHB bus clock.
      
       - Configurations of the AHCI PHY clock, and the signal parameters of
         the GPR13
      
      Setup its own ahci sata driver, contained the imx6q specific
      initialized codes, re-use the generic ahci_platform driver, and keep
      the generic ahci_platform driver clean as much as possible.
      
      tj: patch description reformatted
      Signed-off-by: NRichard Zhu <r65037@freescale.com>
      Reviewed-by: NShawn Guo <shawn.guo@linaro.org>
      Signed-off-by: NTejun Heo <tj@kernel.org>
      9e54eae2