1. 26 9月, 2006 10 次提交
    • A
      [PATCH] Don't leak NT bit into next task · 658fdbef
      Andi Kleen 提交于
      SYSENTER can cause a NT to be set which might cause crashes on the IRET
      in the next task.
      
      Following similar i386 patch from Linus.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      658fdbef
    • J
      [PATCH] i386/x86-64: Work around gcc bug with noreturn functions in unwinder · adf14236
      Jan Beulich 提交于
      Current gcc generates calls not jumps to noreturn functions. When that happens the
      return address can point to the next function, which confuses the unwinder.
      
      This patch works around it by marking asynchronous exception
      frames in contrast normal call frames in the unwind information.  Then teach
      the unwinder to decode this.
      
      For normal call frames the unwinder now subtracts one from the address which avoids
      this problem.  The standard libgcc unwinder uses the same trick.
      
      It doesn't include adjustment of the printed address (i.e. for the original
      example, it'd still be kernel_math_error+0 that gets displayed, but the
      unwinder wouldn't get confused anymore.
      
      This only works with binutils 2.6.17+ and some versions of H.J.Lu's 2.6.16
      unfortunately because earlier binutils don't support .cfi_signal_frame
      
      [AK: added automatic detection of the new binutils and wrote description]
      Signed-off-by: NJan Beulich <jbeulich@novell.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      adf14236
    • A
      [PATCH] Fix a irqcount comment in entry.S · 96e54049
      Andi Kleen 提交于
      Signed-off-by: NAndi Kleen <ak@suse.de>
      96e54049
    • A
      [PATCH] Add a missing check for irq flags tracing in NMI · 7a0a2dff
      Andi Kleen 提交于
      NMIs are not supposed to track the irq flags, but TRACE_IRQS_IRETQ
      did it anyways. Add a check.
      
      Cc: mingo@elte.hu
      Signed-off-by: NAndi Kleen <ak@suse.de>
      7a0a2dff
    • P
      [PATCH] x86: error_code is not safe for kprobes · d28c4393
      Prasanna S.P 提交于
      This patch moves the entry.S:error_entry to .kprobes.text section,
      since code marked unsafe for kprobes jumps directly to entry.S::error_entry,
      that must be marked unsafe as well.
      This patch also moves all the ".previous.text" asm directives to ".previous"
      for kprobes section.
      
      AK: Following a similar i386 patch from Chuck Ebbert
      AK: Also merged Jeremy's fix in.
      
      +From: Jeremy Fitzhardinge <jeremy@goop.org>
      
      KPROBE_ENTRY does a .section .kprobes.text, and expects its users to
      do a .previous at the end of the function.
      
      Unfortunately, if any code within the function switches sections, for
      example .fixup, then the .previous ends up putting all subsequent code
      into .fixup.  Worse, any subsequent .fixup code gets intermingled with
      the code its supposed to be fixing (which is also in .fixup).  It's
      surprising this didn't cause more havok.
      
      The fix is to use .pushsection/.popsection, so this stuff nests
      properly.  A further cleanup would be to get rid of all
      .section/.previous pairs, since they're inherently fragile.
      
      +From: Chuck Ebbert <76306.1226@compuserve.com>
      
      Because code marked unsafe for kprobes jumps directly to
      entry.S::error_code, that must be marked unsafe as well.
      The easiest way to do that is to move the page fault entry
      point to just before error_code and let it inherit the same
      section.
      
      Also moved all the ".previous" asm directives for kprobes
      sections to column 1 and removed ".text" from them.
      Signed-off-by: NChuck Ebbert <76306.1226@compuserve.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      d28c4393
    • A
      [PATCH] Remove obsolete CVS $Id$ from assembler files in arch/x86_64/kernel/* · 44cc4526
      Andi Kleen 提交于
      CVS hasn't been used for a long time for them.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      44cc4526
    • A
      [PATCH] Add some comments to entry.S · 2e91a17b
      Andi Kleen 提交于
      And remove some old obsolete ones.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      2e91a17b
    • A
      [PATCH] Remove all ifdefs for local/io apic · 7f11d8a5
      Andi Kleen 提交于
      IO-APIC or local APIC can only be disabled at runtime anyways and
      Kconfig has forced these options on for a long time now.
      
      The Kconfigs are kept only now for the benefit of the shared acpi
      boot.c code.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      7f11d8a5
    • A
      [PATCH] Add proper alignment to ENTRY · b06babac
      Andi Kleen 提交于
      Previously it didn't align. Use the same one as the C compiler
      in blended mode, which is good for K8 and Core2 and doesn't hurt
      on P4.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      b06babac
    • A
      [PATCH] Clean up asm/smp.h includes · 2f766d16
      Andi Kleen 提交于
      No need to include it from entry.S
      Drop all the #ifdef __ASSEMBLY__
      Signed-off-by: NAndi Kleen <ak@suse.de>
      2f766d16
  2. 31 8月, 2006 1 次提交
  3. 03 8月, 2006 1 次提交
  4. 04 7月, 2006 1 次提交
  5. 01 7月, 2006 1 次提交
  6. 28 6月, 2006 1 次提交
  7. 27 6月, 2006 4 次提交
  8. 31 5月, 2006 1 次提交
  9. 10 4月, 2006 2 次提交
  10. 26 3月, 2006 1 次提交
  11. 15 3月, 2006 1 次提交
  12. 13 3月, 2006 1 次提交
    • A
      [PATCH] x86-64: Fix up handling of non canonical user RIPs · c33d4568
      Andi Kleen 提交于
      EM64T CPUs have somewhat weird error reporting for non canonical RIPs in
      SYSRET.
      
      We can't handle any exceptions there because the exception handler would
      end up running on the user stack which is unsafe.
      
      To avoid problems any code that might end up with a user touched pt_regs
      should return using int_ret_from_syscall.  int_ret_from_syscall ends up
      using IRET, which allows safe exceptions.
      
      Cc: Ernie Petrides <petrides@redhat.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      c33d4568
  13. 18 2月, 2006 1 次提交
  14. 05 2月, 2006 2 次提交
  15. 17 1月, 2006 1 次提交
  16. 12 1月, 2006 5 次提交
  17. 15 11月, 2005 1 次提交
    • J
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      Jacob Shin 提交于
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
      This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
      The user may interface through sysfs files in order to change the threshold configuration.
      
      bank%d/error_count - reads current error count, write to clear.
      bank%d/interrupt_enable - set/clear interrupt enable.
      bank%d/threshold_limit - read/write the threshold limit.
      
      APIC vector 0xF9 in hw_irq.h.
      5 software defined bank ids in mce.h.
      new apic.c function to setup threshold apic lvt.
      defaults to interrupt off, count enabled, and threshold limit max.
      sysfs interface created on /sys/devices/system/threshold.
      
      AK: added some ifdefs to make it compile on UP
      Signed-off-by: NJacob Shin <jacob.shin@amd.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      89b831ef
  18. 13 9月, 2005 2 次提交
    • J
      [PATCH] x86-64: Fix CFI information · 7effaa88
      Jan Beulich 提交于
      Being the foundation for reliable stack unwinding, this fixes CFI unwind
      annotations in many low-level x86_64 routines, plus a config option
      (available to all architectures, and also present in the previously sent
      patch adding such annotations to i386 code) to enable them separatly
      rather than only along with adding full debug information.
      Signed-off-by: NJan Beulich <jbeulich@novell.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      7effaa88
    • A
      [PATCH] x86-64: Make remote TLB flush more scalable · e5bc8b6b
      Andi Kleen 提交于
      Instead of using a global spinlock to protect the state
      of the remote TLB flush use a lock and state for each sending CPU.
      
      To tell the receiver where to look for the state use 8 different
      call vectors.  Each CPU uses a specific vector to trigger flushes on other
      CPUs. Depending on the received vector the target CPUs look into
      the right per cpu variable for the flush data.
      
      When the system has more than 8 CPUs they are hashed to the 8 available
      vectors. The limited global vector space forces us to this right now.
      In future when interrupts are split into per CPU domains this could be
      fixed, at the cost of needing more IPIs in flat mode.
      
      Also some minor cleanup in the smp flush code and remove some outdated
      debug code.
      
      Requires patch to move cpu_possible_map setup earlier.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e5bc8b6b
  19. 10 9月, 2005 1 次提交
  20. 08 9月, 2005 1 次提交
  21. 29 7月, 2005 1 次提交