- 14 11月, 2012 1 次提交
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由 Tero Kristo 提交于
Commit c9e4412a removed all of the USB PHY functions for OMAP4, but this causes a problem with core retention as the MUSB module remains enabled if omap-usb2 phy driver is not used. This keeps the USB DPLL enabled and prevents l3_init pwrdm from idling. Fixed by adding a minimal function back that disables the USB PHY during boot. Signed-off-by: NTero Kristo <t-kristo@ti.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: NFelipe Balbi <balbi@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 07 11月, 2012 1 次提交
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由 Rajendra Nayak 提交于
Remove the FIXME's in the suspend sequence since we now intend to support system level RET support. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com> Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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- 06 11月, 2012 15 次提交
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由 Vishwanath Sripathy 提交于
Add OMAP4460 OPP definitions for voltage and frequencies based on OMAP4460 ES1.0 DM Operating Condition Addendum Version 0.1 The following exceptions are present: * Smartreflex support is still on experimental mode: the gains and min limits are currently pending characterization data. Currently OMAP4430 values are used. * Efuse offset for core OPP100-OV setting is not clear in documentation. * IVA OPPs beyond OPP100 are disabled due to the delta between max OMAP4460 current requirements and Phoenix Max supply on VCORE2 in the default configuration - boards which have supply which can support this should explicitly call opp_enable and enable the same. * MPU OPPs > OPPTURBO can easily be detected using a efuse burnt - currently disabled pending clock changes to support DCC feature. [nm@ti.com: cleanups and updates from Datamanual] Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NVishwanath BS <vishwanath.bs@ti.com> [t-kristo@ti.com: rebased to linux-3.6-rc5] Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
With the new parameters, I2C can now be put to high speed mode for better performance. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
VC code now provides a table of pre-calculated I2C setup parameters, which will be used based on the capacitance value calculated for the I2C trace on the PCB. A default trace length of 6.3cm is used unless board defines its own value during init. The parameters set will be the I2C internal pull setup and the I2C timing parameters for high speed use mode. Full speed mode is not supported as of now. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
RACEN bit should only be set if the voltage and command register addresses are the same. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
This is no longer needed as the ramp times are calculated from voltage deltas + slew rates. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
As vddmin / vddmax voltages for the pmic only describe the pmic capabilities now, change the voltages to be according to spec. TWL data manuals give following values: TWL4030 (SWCS019L) : VDD1: 600mV ... 1450mV, VDD2: 600mV ... 1500mV TWL5030 (SWCS030E) : VDD1: 600mV ... 1450mV, VDD2: 600mV ... 1500mV TWL6030 (SWCS045A) : 0V ... 2100mV Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
We now use the previously defined oscillator setup / shutdown times to calculate the register values for CLKSETUP. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
Now we select the vddmin and vddmax values based on both pmic and voltage processor data, this allows usage of different power ICs. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
This contains startup and shutdown times for the oscillator. By default use ULONG_MAX. Oscillator setup is used for calculating and setting up latencies for sleep modes that disable oscillator. Based on a patch from Nishanth Menon <nm@ti.com>. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
OMAP4 VC code now uses voltage deltas + slew rates for calculating actual ramp times for voltage changes. Both retention / sleep + off mode voltage ramp times are setup at the same time during initialization. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
OMAP4 has two VOLTSETUP registers. One is controlling retention and sleep voltage setup times, the other one off mode setup times. Both of these need to be setup for stable behavior of the device. The code setting up the new register will be added in the next patch. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
OMAP3 VC code now uses voltage deltas + slew rates for calculating actual ramp times for voltage changes. Previously a static value was used. Two calculation methods are provided: i2c_timings and off_timings. I2C timings are used during retention or off mode transition which is initiated over I2C, and OFF timings are used if PMIC signal (nsleep) is used to control all the off mode voltages at the same time. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
These new structs will hold the sleep voltage levels (omap_vc_params) and voltage processor min / max voltages (omap_vp_params.) Previously these were part of the PMIC struct, but they do not really belong there, as they are OMAP chip specific, not PMIC specific parameters. voltdm code is also changed to use the new structs. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tero Kristo 提交于
These are now called vddmin and vddmax, as these fields will be used globally for selecting voltage ranges for a pmic channel, and not only for voltage processor. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Nishanth Menon 提交于
Every PMIC has it's own eccentricities, For example, one of the PMIC has MSB set to 1 for a specific function - voltage enable! using an hardcoded value specific for TWL when copied over to such an implementation causes the system to crash as the MSB bit was 0 and the voltage got disabled!. Instead we use actual values and depend on the convertion routines to abstract out the eccentricities of each PMIC. With this, we can now move the voltages to a common location in voltage.h as they are no longer dependent on PMICs and expect the PMIC's conversion routines to set a cap if the voltage is out of reach for the PMIC. Reported-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NVishwanath BS <vishwanath.bs@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 26 10月, 2012 1 次提交
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由 Nishanth Menon 提交于
change pr_warnings to pr_warn and ensure a newline is present in all messages Cc: linux-omap@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 24 10月, 2012 1 次提交
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由 Vaibhav Hiremath 提交于
ARM: AM33XX: Fix configuration of dmtimer parent clock by dmtimer driverDate:Wed, 17 Oct 2012 13:55:55 -0500 Add dmtimer clock aliases for AM33XX devices so that the parent clock for the dmtimer can be set correctly by the dmtimer driver. Without these clock aliases the dmtimer driver will fail to find the parent clocks for the dmtimer. Verified that DMTIMERs can be successfully requested on AM335x beagle bone. Original patch was provided by Vaibhav Hiremath [1]. Changelog and additional verification performed by Jon Hunter. [1] http://marc.info/?l=linux-omap&m=134693631608018&w=2Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: NJon Hunter <jon-hunter@ti.com> Tested-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 10月, 2012 5 次提交
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由 Kevin Hilman 提交于
After commit 24d7b40a (ARM: OMAP2+: PM: MPU DVFS: use generic CPU device for MPU-SS), OPPs are registered using an existing CPU device, not the omap_device for MPU-SS. First, fix the board file to use get_cpu_device() as required by the above commit, otherwise custom OPPs will be added to the wrong device. Second, the board files OPP init is called from the its init_machine method, and the generic CPU devices are not yet created when init_machine is run. Therefore OPP initialization will fail. To fix, use a device_initcall() for the board file's OPP customization, and make the device_initcall board-specific by using a machine_is check. Reported-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Tony Lindgren 提交于
On n900 uart1 pins are not not used for uart, instead they are used to connect to a cell modem over ssi. Looks like we're currently missing these signal names for 3430 for some reason, and only have some of them listed for 3630. Obviously the signals are there for 3430 if n900 is using them and they are documented in some TRMs. Note that these will eventually be replaced by device tree based pinctrl-single.c driver. But for now these are needed to verify the SSI pins for devices like Nokia N900. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Commit 8f31cefe (ARM: OMAP2+: select PINCTRL in Kconfig) added select PINCTRL, but accdentally added it to a wrong location. We want to select if for ARCH_OMAP2PLUS, not for ARCH_OMAP2PLUS_TYPICAL. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Kevin Hilman 提交于
The runtime PM framework assumes that the hardware state of devices when initialized is disabled. For all omap_devices, we idle/disable device by default. However, the console uart uses a "no idle" option during omap_device init in order to allow earlyprintk usage to work seamlessly during boot. Because the hardware is left partially enabled after init (whatever the bootloader settings were), the omap_device should later be fully initialized (including mux) and the runtime PM framework should be told that the device is active, and not disabled so that the hardware state is in sync with runtime PM state. To fix, after the device has been created/registered, call omap_device_enable() to finialize init and use pm_runtime_set_active() to tell the runtime PM core the device is enabled. Tested on 2420/n810, 3530/Overo, 3530/Beagle, 3730/OveroSTORM, 3730/Beagle-xM, 4460/PandaES. Suggested-by: NRussell King <rmk+kernel@arm.linux.org.uk> Cc: Felipe Balbi <balbi@ti.com> Cc: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Paul Walmsley 提交于
On OMAP34xx/35xx, and OMAP36xx chips with ES < 1.2, if the PER powerdomain goes to OSWR or OFF while CORE stays at CSWR or ON, or if, upon chip wakeup from OSWR or OFF, the CORE powerdomain goes ON before PER, the UART3/4 FIFOs and McBSP2/3 SIDETONE memories will be unusable. This is erratum i582 in the OMAP36xx Silicon Errata document. This patch implements one of several parts of the workaround: the addition of the wakeup dependency between the PER and WKUP clockdomains, such that PER will wake up at the same time CORE_L3 does. This is not a complete workaround. For it to be complete: 1. the PER powerdomain's next power state must not be set to OSWR or OFF if the CORE powerdomain's next power state is set to CSWR or ON; 2. the UART3/4 FIFO and McBSP2/3 SIDETONE loopback tests should be run if the LASTPOWERSTATEENTERED bits for PER and CORE indicate that PER went OFF while CORE stayed on. If loopback tests fail, then those devices will be unusable until PER and CORE can undergo a transition from ON to OSWR/OFF and back ON. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 18 10月, 2012 2 次提交
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由 Jon Hunter 提交于
Currently, if the GPMC driver fails to reserve memory when probed we will call BUG() and the kernel will not boot. Instead of calling BUG(), return an error from probe and allow kernel to boot. Boot tested on AM335x beagle bone board and OMAP4430 Panda board. V2 changes: - Ensure that clock and memory resources are released on error. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tero Kristo 提交于
Previously the code only acquired spinlock after increasing / decreasing the usecount value, which is wrong. This leaves a small window where a task switch may occur between the check of the usecount and the actual wakeup / sleep of the domain. Fixed by moving the spinlock locking before the usecount access. Left the usecount as atomic_t if someone wants an easy access to the parameter through atomic_read. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 17 10月, 2012 3 次提交
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由 Sebastien Guiriec 提交于
Correct DMIC hwmod lockup error message and replace printk() by pr_err(). Signed-off-by: NSebastien Guiriec <s-guiriec@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Benoit Cousson 提交于
The GPMC code has been converted to a driver by the following commit: commit da496873 Author: Afzal Mohammed <afzal@ti.com> Date: Sun Sep 23 17:28:25 2012 -0600 ARM: OMAP2+: gpmc: minimal driver support It now requests a clock with con-id "fck" otherwise the probe will fails. [ 0.342010] omap-gpmc omap-gpmc: error: clk_get [ 0.346771] omap-gpmc: probe of omap-gpmc failed with error -2 Add the "omap-gmpc" dev-id and fck con-id to the already existing gmpc-fck dummy clock. Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Afzal Mohammed <afzal@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Tony Lindgren 提交于
Commit 7d7e1eba (ARM: OMAP2+: Prepare for irqs.h removal) changed the interrupts to allow enabling sparse IRQ, but accidentally added the omap3 INTC base to the local IRQ. This causes the following: twd: can't register interrupt 45 (-22) twd_local_timer_register failed -22 The right fix is to not add any base, as it is a local timer. For the OMAP44XX_IRQ_LOCALWDT we had defined earlier there are no users, so no need to fix that. Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 16 10月, 2012 2 次提交
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由 Jean Pihet 提交于
Remove the device dependent code (ex. cpu_is_xxx()) and settings from the driver code and instead pass them via the platform data. This allows a clean separation of the driver code and the platform code, as required by the move of the platform header files to include/linux/platform_data. Note about the smartreflex functional clocks: the smartreflex fclks are derived from sys_clk and have the same name as the main_clk from the hwmod entry, in order for the SmartReflex driver to request the fclk (using clk_get(dev, "fck")). Signed-off-by: NJean Pihet <j-pihet@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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由 Jean Pihet 提交于
Rename the smartreflex fck names for consistency and better readability; rename the clock aliases so that they match the hwmod main_clk names. Signed-off-by: NJean Pihet <j-pihet@ti.com> Signed-off-by: NKevin Hilman <khilman@ti.com>
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- 14 10月, 2012 1 次提交
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由 Russell King 提交于
As suggested by Andrew Morton: This is a pet peeve of mine. Any time there's a long list of items (header file inclusions, kconfig entries, array initalisers, etc) and someone wants to add a new item, they *always* go and stick it at the end of the list. Guys, don't do this. Either put the new item into a randomly-chosen position or, probably better, alphanumerically sort the list. lets sort all our select statements alphanumerically. This commit was created by the following perl: while (<>) { while (/\\\s*$/) { $_ .= <>; } undef %selects if /^\s*config\s+/; if (/^\s+select\s+(\w+).*/) { if (defined($selects{$1})) { if ($selects{$1} eq $_) { print STDERR "Warning: removing duplicated $1 entry\n"; } else { print STDERR "Error: $1 differently selected\n". "\tOld: $selects{$1}\n". "\tNew: $_\n"; exit 1; } } $selects{$1} = $_; next; } if (%selects and (/^\s*$/ or /^\s+help/ or /^\s+---help---/ or /^endif/ or /^endchoice/)) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } undef %selects; } print; } if (%selects) { foreach $k (sort (keys %selects)) { print "$selects{$k}"; } } It found two duplicates: Warning: removing duplicated S5P_SETUP_MIPIPHY entry Warning: removing duplicated HARDIRQS_SW_RESEND entry and they are identical duplicates, hence the shrinkage in the diffstat of two lines. We have four testers reporting success of this change (Tony, Stephen, Linus and Sekhar.) Acked-by: NJason Cooper <jason@lakedaemon.net> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 10月, 2012 8 次提交
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由 Paul Walmsley 提交于
Commit eb05f691 ("ARM: OMAP: hwmod: partially un-reset hwmods might not be properly enabled") added code to skip the IP block disable sequence if all of the block's hardreset lines weren't asserted. But this did not handle the case when no hardreset lines were associated with a module, which is the general case. In that situation, the IP block disable would be skipped. This is likely to cause PM regressions. So, modify _omap4_disable_module() and _am33xx_disable_module() to only bail out early if there are any hardreset lines asserted. And move the AM33xx test above the actual module disable code to ensure that the behavior is consistent. Reported-by: NArchit Taneja <a0393947@ti.com> Tested-by: Archit Taneja <a0393947@ti.com> # DSS Cc: Omar Ramirez Luna <omar.luna@linaro.org> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: NVaibhav Hiremath <hvaibhav@ti.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com> # AM335x Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jon Hunter 提交于
Commit b71c7217 (ARM: OMAP2+: clockdomain/hwmod: add workaround for EMU clockdomain idle problems) added a workaround for the EMU clock domain on OMAP3/4 devices to prevent the clock domain for transitioning while it is in use. In the proposed patch [1] code was added to the omap3xxx_clkdm_clk_enable() and omap3xxx_clkdm_clk_disable() functions to check for the flag CLKDM_MISSING_IDLE_REPORTING and perform the appropriate action. However, in the merged patch it appears that this code was added to the omap2_clkdm_clk_enable() and omap2_clkdm_clk_disable() functions by mistake. [1] http://marc.info/?l=linux-arm-kernel&m=134383567112518&w=2Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Vikram Narayanan 提交于
Use the enum for board_ref_clock from linux/wl12xx.h Signed-off-by: NVikram Narayanan <vikram186@gmail.com> Cc: linux-omap@vger.kernel.org Reviewed-by: Pankaj Jangra<jangra.pankaj9@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Wei Yongjun 提交于
Remove duplicated include. dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Senna Tschudin 提交于
Found by http://coccinelle.lip6.fr/Signed-off-by: NPeter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
u-boot stopped configuring 'non essential' pins recently. These pins are essential for audio and need to be done to have working audio on the board. Pin Mux configuration for: twl6040 audpwron gpio, McPDM, and McBSP1. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Peter Ujfalusi 提交于
u-boot stopped configuring 'non essential' pins recently. These pins are essential for audio and need to be done to have working audio on the board. Pin Mux configuration for: twl6040 audpwron gpio, McPDM, DMIC, McBSP1 and McBSP2. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Raphael Assenat 提交于
This patch adds a missing hwmod entry for the HDQ/1-Wire module present in the AM3505/17 CPUs. This restores 1-Wire support to our AM3505 boards. We think it probably stopped working with commit 96b1b29d ARM: OMAP2+: HDQ1W: use omap_device Signed-off-by: NRaphael Assenat <raph@8d.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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