1. 02 6月, 2015 1 次提交
  2. 01 6月, 2015 1 次提交
  3. 30 4月, 2015 1 次提交
  4. 27 4月, 2015 10 次提交
  5. 02 4月, 2015 1 次提交
  6. 30 3月, 2015 3 次提交
  7. 24 3月, 2015 1 次提交
  8. 17 3月, 2015 3 次提交
  9. 16 3月, 2015 1 次提交
  10. 12 3月, 2015 1 次提交
    • S
      ARM: Kirkwood: add DT description for nas2big · 0c2d652f
      Simon Guinot 提交于
      This patch adds the DT description for the LaCie "2Big NAS" (nas2big).
      This NAS is an hardware upgrade of the 2Big Network v2.
      
      Chipset and device list:
      
      - CPU Marvell 88F6282 1600Mhz
      - SDRAM memory, 256MB DDR3 (2x128MB x8) 533Mhz
      - 1 Ethernet Gigabit port (PHY Marvell 88E1518)
      - Flash memory, NAND 256MB TSOP48
      - I2C EEPROM, 512 bytes (AT24 type)
      - PCIe SATA controller JMicron JMB360 (eSATA)
      - I2C fan controller GMT G762 (with a separate alarm GPIO)
      - 1 USB2 host port
      - 1 push button
      - 1 power switch
      - 2 SATA LEDs (bi-color, blue and red)
      - 1 power LED (bi-color, blue and red)
      - CPLD for LEDs and start-up management (Altera Max EMP3064)
      Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org>
      Acked-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      0c2d652f
  11. 07 3月, 2015 1 次提交
  12. 05 3月, 2015 1 次提交
  13. 04 3月, 2015 1 次提交
    • T
      ARM: mvebu: add Device Tree files for Armada 39x SoC and board · 538da83d
      Thomas Petazzoni 提交于
      This commit adds the Device Tree files for the Armada 39x family of
      processors, as well as one Armada 398 Development Board.
      
      Like for other Marvell EBU families, a common armada-39x.dtsi contains
      the description of the common features of all Armada 39x SoCs, while
      armada-390.dtsi and armada-398.dtsi respectively describe the
      specificities of those SoCs.
      
      Finally, an armada-398-db.dts file is added to describe the Armada 398
      Development Board itself.
      
      So far, the following features are supported:
      
       * SMP: dual Cortex-A9
       * Basic ARM IPs: SCU, timer, GIC, L2 cache
       * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus
         controller, MPIC interrupt controller, timer, CPU reset for SMP,
         PMSU.
       * I2C
       * SPI
       * SDHCI
       * XOR
       * NAND
       * UART
       * PCIe
      
      Additional features will be supported in the future.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      538da83d
  14. 03 3月, 2015 1 次提交
  15. 02 3月, 2015 1 次提交
  16. 01 3月, 2015 1 次提交
  17. 27 2月, 2015 1 次提交
  18. 24 2月, 2015 5 次提交
  19. 30 1月, 2015 1 次提交
  20. 27 1月, 2015 1 次提交
  21. 26 1月, 2015 2 次提交
  22. 24 1月, 2015 1 次提交