- 27 8月, 2008 1 次提交
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由 Bryan Wu 提交于
Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 06 8月, 2008 1 次提交
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由 Michael Hennerich 提交于
- Disable all bits in SIC_IWR unless we are going into a real (DPMC) power saving mode. Any Interrupt can wake the core form it's idle state. - Remove deep sleep mode as it is not going to be used anywhere: We support sleep, sleep deeper and hibernate. Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 19 7月, 2008 1 次提交
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由 Michael Hennerich 提交于
Enable: PM_SUSPEND_MEM -> Blackfin Hibernate to SDRAM This feature requires a special bootloader (u-boot) supporting return from hibernate. Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 07 5月, 2008 1 次提交
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由 Michael Hennerich 提交于
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 09 2月, 2008 1 次提交
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由 Michael Hennerich 提交于
- Add support for irq_wake on system and gpio interrupts - Remove outdated kernel options - Add option to select default PM mode - Fix various places where SIC_IWRx was only handled partially Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 08 5月, 2007 1 次提交
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由 Bryan Wu 提交于
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NMariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: NAubrey Li <aubrey.li@analog.com> Signed-off-by: NJie Zhang <jie.zhang@analog.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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