Fixes an issue found on rockchip rk3036 and rk3188 SOC platforms. For
some reason, the existing msleep(25) is not enough after the force mode.
The following patch was reported to fix the issue.

This does increase the probe delay again slightly, but not up to the
level it was before the original series of patches that this fixes. It
does not cause any other issues when tested on Synopsys HAPS and Altera
socfpga platforms.

Need to revisit this series next release to see if we can address these
issues without having an unconditional delay.

Fixes: 09c96980 ("usb: dwc2: Add functions to set and clear force mode")
Reported-by: NCaesar Wang <caesar.upstream@gmail.com>
Reported-by: NMichael Niewoehner <linux@mniewoehner.de>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NCaesar Wang <caesar.upstream@gmail.com>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@kernel.org>

Fixes an issue found on Raspberry PI platform that prevents probe. Don't
skip setting the force mode if it's already set.

Fixes: 09c96980 ("usb: dwc2: Add functions to set and clear force mode")
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Reported-by: NStefan Wahren <stefan.wahren@i2se.com>
Reported-by: NRemi Pommarel <repk@triplefau.lt>
Tested-by: NStefan Wahren <stefan.wahren@i2se.com>
Tested-by: NRemi Pommarel <repk@triplefau.lt>
Signed-off-by: NFelipe Balbi <balbi@kernel.org>

This reverts commit 263b7fb5 ("usb: dwc2: Move reset into
dwc2_get_hwparams()") due to regression found on bcm2835 platform. USB
ethernet fails, due to being unable to pick up proper parameters when
performing a plain reset before reading hw params.

Below shows the results of the gnptxfsiz and hptxfsiz with and before
and after reverting this (from Stefan Wahren):

So here is the probe result before Patch 1 is applied:

[    1.283148] dwc2 20980000.usb: Configuration mismatch. dr_mode forced to host
[    1.313894] dwc2 20980000.usb: gnptxfsiz=00201000
[    1.314104] dwc2 20980000.usb: hptxfsiz=00000000
[    1.353908] dwc2 20980000.usb: 256 invalid for host_nperio_tx_fifo_size. Check HW configuration.
[    1.354262] dwc2 20980000.usb: 512 invalid for host_perio_tx_fifo_size. Check HW configuration.
[    1.394249] dwc2 20980000.usb: DWC OTG Controller
[    1.394561] dwc2 20980000.usb: new USB bus registered, assigned bus number 1
[    1.394917] dwc2 20980000.usb: irq 33, io mem 0x00000000

And here is the probe result after Patch 1 is applied:

[    1.280107] dwc2 20980000.usb: Configuration mismatch. dr_mode forced to host
[    1.353949] dwc2 20980000.usb: gnptxfsiz=01001000
[    1.354166] dwc2 20980000.usb: hptxfsiz=02002000
[    1.434301] dwc2 20980000.usb: DWC OTG Controller
[    1.434616] dwc2 20980000.usb: new USB bus registered, assigned bus number 1
[    1.434973] dwc2 20980000.usb: irq 33, io mem 0x00000000
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Reported-by: NStefan Wahren <stefan.wahren@i2se.com>
Reported-by: NRemi Pommarel <repk@triplefau.lt>
Tested-by: NStefan Wahren <stefan.wahren@i2se.com>
Tested-by: NRemi Pommarel <repk@triplefau.lt>
Signed-off-by: NFelipe Balbi <balbi@kernel.org>

The delay for force mode is only 25ms according to the databook.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Adds separate functions to get the host and device specific hardware
parameters. The functions check whether the parameters need to be read
at all, depending on dr_mode, and forces the mode only if necessary.
This saves some delays during probe. This also adds two device mode
parameters that will be used by the gadget.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Added functions to set force mode for host and device. These functions
will check the current mode and only force if needed thus avoiding
unnecessary force mode delays. However clearing the mode is currently
done unconditionally and with the delay in place. This is needed during
the connector ID status change interrupt in order to ensure that the
mode has changed properly. This preserves the old behavior only for this
case. The warning comment about this is moved into the clear mode
condition.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

The reset is required to get reset values of the hardware parameters but
the force mode is not. Move the base reset into dwc2_get_hwparams() and
do the reset and force mode afterwards.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Added functions to query the GHWCFG2.OTG_MODE. This tells us whether the
controller hardware is configured for OTG, device-only, or host-only.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

dwc2_core_reset() was previously renamed to
dwc2_core_reset_and_dr_force_mode(). Now add back dwc2_core_reset() which
performs only a basic core reset without forcing the mode.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Renamed dwc2_core_reset() to dwc2_core_reset_and_force_dr_mode(). This
describes what it is doing more accurately. This is in preparation of
introducing a plain dwc2_core_reset() function that only performs the
reset and doesn't force the mode.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Calls to dwc2_core_reset() are currently very slow, taking at least
150ms (possibly more).  It behooves us to take as many of these calls
out as possible.

It turns out that the calls in dwc2_fs_phy_init() and dwc2_hs_phy_init()
should (as documented in the code) only be needed if we need to do a PHY
SELECT.  That means that if we see that we can avoid the PHY SELECT then
we can avoid the reset.

This patch appears to successfully bypass two resets (one per USB
device) on rk3288-based ARM Chromebooks.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

I found that the probe function of dwc2 driver takes much time
when kernel boot up. There are many long delays in the probe
function these take almost 1 second.

This patch trying to reduce unnecessary delay time.

In dwc2_core_reset() I see it use two at least 20ms delays to
wait AHB idle and core soft reset, but dwc2 data book said that
dwc2 core soft reset and AHB idle just need a few clocks (I think
it refers to AHB clock, and AHB clock run at 150MHz in my RK3288
board), so 20ms is too long, delay 1us for wait AHB idle and soft
reset is enough.

And in dwc2_get_hwparams() it takes 150ms to wait ForceHostMode
and ForceDeviceMode valid but in data book it said software must
wait at least 25ms before the change to take effect, so I reduce
this time to 25ms~50ms. By the way, is there any state bit show
that the force mode take effect ? Could we poll curmod bit for
figuring out if the change take effect ?

It seems that usleep_range() at boot time will pick the longest
value in the range. In dwc2_core_reset() there is a very long
delay takes 200ms, and this function run twice when probe, could
any one tell me is this delay time resonable ?

I have tried this patch in my RK3288-evb board. It works well.
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

On some host-only DWC2 ports (like the one in rk3288) when we set
GUSBCFG_FORCEHOSTMODE in GUSBCFG and then read back, we don't see the
bit set.  Presumably that's because the port is always forced to HOST
mode so there's no reason to implement these status bits.

Since we know dwc2_core_reset() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

In (usb: dwc2: reset dwc2 core before dwc2_get_hwparams()) we added an
extra reset to the probe path for the dwc2 USB controllers.  This
allowed proper detection of parameters even if the firmware had already
used the USB part.

Unfortunately, this extra reset is quite slow and is affecting boot
speed.  We can avoid the double-reset by skipping the extra reset that
would happen just after the one we added.  Logic that explains why this
is safe:

* As of the CL mentioned above, we now always call dwc2_core_reset() in
  dwc2_driver_probe() before dwc2_hcd_init().

* The only caller of dwc2_hcd_init() is dwc2_driver_probe(), so we're
  guaranteed that dwc2_core_reset() was called before dwc2_hdc_init().

* dwc2_hdc_init() is the only caller that passes an irq other than -1 to
  dwc2_core_init().  Thus if dwc2_core_init() is called with an irq
  other than -1 we're guaranteed that dwc2_core_reset was called before
  dwc2_core_init().

...this allows us to remove the dwc2_core_reset() in dwc2_core_init() if
irq is not < 0.

Note that since "irq" wasn't used in the function dwc2_core_init()
anyway and since select_phy was always set at exactly the same times we
could avoid the reset, we remove "irq" and rename "select_phy" to
"initial_setup" and adjust the callers accordingly.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

We initiate dwc2 usb controller in BIOS, dwc2_core_reset() should
be called before dwc2_get_hwparams() to reset core registers to
default value. Without this the FIFO setting might be incorrect
because calculating FIFO size need power-on value of
GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.

This patch could avoid warnning massage like in rk3288 platform:
[    2.074764] dwc2 ff580000.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Previously dwc2_get_hwparams() was changing GUSBCFG and not putting it
back the way it was (specifically it set and cleared FORCEHOSTMODE).
Since we want to move dwc2_core_reset() _before_ dwc2_get_hwparams() we
should make sure dwc2_get_hwparams() isn't messing with things in a
permanent way.

Since we're now looking at GUSBCFG, it's obvious that we shouldn't need
all the extra delays if FORCEHOSTMODE was already set.  This will avoid
some delays for any ports that have forced host mode.
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

In some cases, like when you've got a "Microsoft Wireless Keyboard 2000"
connected to dwc2 with a hub, expected that we'll get some transfer
errors sometimes.  The controller is expected to try at least 3 times
before giving up.  See figure "Figure A-67. Normal HS CSPLIT 3 Strikes
Smash" in the USB spec.

The dwc2 controller has a way to support this by using the "EC_MC"
field.  The Raspberry Pi driver has logic for setting this right.  See
fiq_fsm_queue_split_transaction() in their "dwc_otg_hcd.c".  Let's use
the same logic.

After making this change, we no longer get dropped characters from the
above mentioned keyboard.  Other devices on the same bus as the keyboard
also behave more properly.

Thanks for Julius Werner for the expert analysis and suggestions.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Masks for HCDMA.CTD and HCDMA.DMAAddr are incorrect. As we always
start from first descriptor, no need to mask the address anyway.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Use Streaming DMA mappings to handle cache coherency of frame list and
descriptor list. Cache are always flushed before controller access it
or before cpu access it.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

As descriptor dma mode does not support split transfers, it can't be
enabled for high speed devices. Add a core parameter to enable it for
full speed devices.

Ensure frame list and descriptor list are correctly freed during
disconnect.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Fix a duplicate argument warning reported by 0-DAY kernel test
infrastructure in the following patch:
77dbf713 usb: dwc2: host: add disconnect interrupt to host only interrupts
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

If an interrupt rises during hibernation process, dwc2 will assert
interrupt line to interrupt controller. If interrupt is level
sensitive, interrupt handler will be called in a loop because dwc2
will not be able to clear it while controller is hibernated.
Thus, clear all controller interrupts before hibernation entry.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

GINTSTS.DisconnInt is host only interrupt and should be disable after
dwc2_disable_host_interrupts is called.
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Frame number is reset in hardware after exiting hibernation.
Thus, reset frame_number and ensure qh are queued with correct
sched_frame.

Otherwise, qh->sched_frame may be too high compared to
current frame number (which is 0). This can delay addition of qh in
the list of transfers until frame number reaches qh->sched_frame.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

When entering hibernation hprt0 must be read using dwc2_read_hprt0().
Otherwise, any set hprt0 status bits will be cleared when restoring
hprt0 on exit from hibernation.
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Tested-by: NRobert Baldyga <r.baldyga@samsung.com>
Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by: NJohn Youn <johnyoun@synopsys.com>
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch switches calls to readl/writel to their
dwc2_readl/dwc2_writel equivalents which preserve platform endianness.

This patch is necessary to access dwc2 registers correctly on big-endian
systems such as the mips based SoCs made by Lantiq. Then dwc2 can be
used to replace ifx-hcd driver for Lantiq platforms found e.g. in
OpenWrt.

The patch was autogenerated with the following commands:
$EDITOR core.h
sed -i "s/\<readl\>/dwc2_readl/g" *.c hcd.h hw.h
sed -i "s/\<writel\>/dwc2_writel/g" *.c hcd.h hw.h

Some files were then hand-edited to fix checkpatch.pl warnings about
too long lines.
Signed-off-by: NAntti Seppälä <a.seppala@gmail.com>
Signed-off-by: NVincent Pelletier <plr.vincent@gmail.com>
Signed-off-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This patch fix spelling typo inv various part of sources.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Acked-by: NRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: NJiri Kosina <jkosina@suse.com>

Register backup function can be called from atomic context. Instead
of using atomic memory pool, embed backup storage space in
struct dwc2_hsotg.

Also add a valid flag in each struct as NULL pointer can't be used as
the content validity check any more.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

dwc2 may not be able to exit from hibernation if the hardware
does not provide a way to detect resume signalling in this state.
Thus, add the possibility to disable hibernation feature.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

As dwc2 pci module is now exporting dwc2 platform device, include
platform.o in dwc2-y and remove USB_DWC2_PLATFORM configuration
option. Driver will be built as two modules, dwc2.ko and dwc2_pci.ko.
dwc2.ko is the new platform driver.

Remove all EXPORT_SYMBOL_GPL as they are not needed any more.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

So the parameters can be used in both host and gadget modes.
Also consolidate param functions in the core.h
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NMian Yousaf Kaukab <yousaf.kaukab@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

This is required due to an Intel specific hardware issue. Where id-
pin setup causes glitches on the interrupt line when CONIDSTSCHG
interrupt is enabled.

Specify external_id_pin_ctl when an external driver (for example phy)
can handle id change, so that CONIDSTSCHG interrupt can be disabled
from the controller.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

When suspending usb bus, phy driver may disable controller power.
In this case, registers need to be saved on suspend and restored
on resume.
Acked-by: NJohn Youn <johnyoun@synopsys.com>
Signed-off-by: NGregory Herrero <gregory.herrero@intel.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Fixed 3 typos in comments
Signed-off-by: NMickael Maison <mickael.maison@gmail.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Make dwc2_handle_common_intr call the gadget interrupt function when operating
in peripheral mode. Remove the spinlock functions in s3c_hsotg_irq as
dwc2_handle_common_intr() already has the spinlocks.

Move the registeration of the IRQ to common code for platform and PCI.

Remove duplicate interrupt conditions that was in gadget, as those are handled
by dwc2 common interrupt handler.
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

Clip max_transfer_size to 65535 for host. dwc2_hc_setup_align_buf()
allocates coherent buffers with this size, and if it's too large we
can exhaust the coherent DMA pool.

Tested on Raspberry Pi and Altera SOCFPGA.
Signed-off-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

According to the "dr_mode", the otg controller can work as
device role and host role. Some boards always want to use host mode
and some other boards want to use gadget mode. We use the dts setting
to set dwc2's mode, rather than fixing it to whatever hardware says.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The documentation for GNPTXFSIZ says that "For host mode, this field
is always valid."  Since we're already switching to host mode for
HPTXFSIZ, let's also read GNPTXFSIZ in host mode.

On an rk3288 SoC, without this change we see this at bootup:
  dwc2 ff580000.usb: gnptxfsiz=00100400
  dwc2 ff580000.usb: 128 invalid for host_nperio_tx_fifo_size. Check HW configuration.

After this change we see:
  dwc2 ff580000.usb: gnptxfsiz=04000400
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver cannot just use the fifo sizes
as read from those registers.

For platforms that face the same issue, this commits sets the RX, periodic TX,
and non-periodic TX fifo size to those that are recommended v2.93a spec for
the DWC2 IP. Implements Method #2 from the Synopsys v2.93a spec for the DWC2.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NPaul Zimmerman <paulz@synopsys.com>
Reviewed-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>