1. 01 10月, 2013 2 次提交
  2. 31 8月, 2013 2 次提交
    • A
      drm/edid: add a helper function to extract the speaker allocation data block (v3) · d105f476
      Alex Deucher 提交于
      This adds a helper function to extract the speaker allocation
      data block from the EDID.  This data block describes what speakers
      are present on the display device.
      
      v2: update per Ville Syrjälä's comments
      v3: fix copy/paste typo in memory allocation
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Tested-by: NRafał Miłecki <zajec5@gmail.com>
      d105f476
    • A
      drm/edid: add quirk for Medion MD30217PG · 118bdbd8
      Alex Deucher 提交于
      This LCD monitor (1280x1024 native) has a completely
      bogus detailed timing (640x350@70hz).  User reports that
      1280x1024@60 has waves so prefer 1280x1024@75.
      
      Manufacturer: MED  Model: 7b8  Serial#: 99188
      Year: 2005  Week: 5
      EDID Version: 1.3
      Analog Display Input,  Input Voltage Level: 0.700/0.700 V
      Sync:  Separate
      Max Image Size [cm]: horiz.: 34  vert.: 27
      Gamma: 2.50
      DPMS capabilities: Off; RGB/Color Display
      First detailed timing is preferred mode
      redX: 0.645 redY: 0.348   greenX: 0.280 greenY: 0.605
      blueX: 0.142 blueY: 0.071   whiteX: 0.313 whiteY: 0.329
      Supported established timings:
      720x400@70Hz
      640x480@60Hz
      640x480@72Hz
      640x480@75Hz
      800x600@56Hz
      800x600@60Hz
      800x600@72Hz
      800x600@75Hz
      1024x768@60Hz
      1024x768@70Hz
      1024x768@75Hz
      1280x1024@75Hz
      Manufacturer's mask: 0
      Supported standard timings:
      Supported detailed timing:
      clock: 25.2 MHz   Image Size:  337 x 270 mm
      h_active: 640  h_sync: 688  h_sync_end 784 h_blank_end 800 h_border: 0
      v_active: 350  v_sync: 350  v_sync_end 352 v_blanking: 449 v_border: 0
      Monitor name: MD30217PG
      Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz
      Serial No: 501099188
      EDID (in hex):
                00ffffffffffff0034a4b80774830100
                050f010368221b962a0c55a559479b24
                125054afcf00310a0101010101018180
                000000000000d60980a0205e63103060
                0200510e1100001e000000fc004d4433
                3032313750470a202020000000fd0038
                4c1e530e000a202020202020000000ff
                003530313039393138380a2020200078
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      Reported-by: friedrich@mailstation.de
      Cc: stable@vger.kernel.org
      118bdbd8
  3. 30 8月, 2013 8 次提交
  4. 08 8月, 2013 3 次提交
  5. 04 7月, 2013 1 次提交
  6. 27 6月, 2013 1 次提交
  7. 11 6月, 2013 1 次提交
    • V
      drm/edid: Add both 60Hz and 59.94Hz CEA modes to connector's mode list · e6e79209
      Ville Syrjälä 提交于
      Having both modes can be beneficial for video playback cases. If you can
      match the video framerate exactly, and the audio and video clocks come
      from the same source, you should be able to avoid dropped/repeated
      frames without expensive operations such as resampling the audio to
      match video output rate.
      
      Rather than add both variants based on the CEA extension short video
      descriptors in do_cea_modes(), add only one variant there. Once all
      the EDID has been fully probed, do a loop over the entire probed mode
      list, during which we add the other variants for all modes that match
      CEA modes. This allows us to match modes that didn't come via the CEA
      short video descriptors. For example one Samsung TV here doesn't have
      the 640x480-60 mode as a SVD, but instead it's specified via a detailed
      timing descriptor.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDave Airlie <airlied@redhat.com>
      e6e79209
  8. 26 4月, 2013 2 次提交
  9. 24 4月, 2013 1 次提交
  10. 24 3月, 2013 2 次提交
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  15. 20 1月, 2013 1 次提交
  16. 29 11月, 2012 1 次提交
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  19. 03 10月, 2012 2 次提交
  20. 26 9月, 2012 1 次提交
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  22. 13 9月, 2012 2 次提交