1. 29 11月, 2014 1 次提交
  2. 26 11月, 2014 1 次提交
  3. 19 8月, 2014 2 次提交
  4. 19 5月, 2014 1 次提交
  5. 05 2月, 2014 1 次提交
    • S
      DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs · 006e983b
      Sricharan R 提交于
      In some socs the gic can be preceded by a crossbar IP which
      routes the peripheral interrupts to the gic inputs. The peripheral
      interrupts are associated with a fixed crossbar input line and the
      crossbar routes that to one of the free gic input line.
      
      The DT entries for peripherals provides the fixed crossbar input line
      as its interrupt number and the mapping code should associate this with
      a free gic input line. This patch adds the support inside the gic irqchip
      to handle such routable irqs. The routable irqs are registered in a linear
      domain. The registered routable domain's callback should be implemented
      to get a free irq and to configure the IP to route it.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Signed-off-by: NSricharan R <r.sricharan@ti.com>
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      006e983b
  6. 22 12月, 2013 1 次提交
  7. 24 9月, 2013 2 次提交
  8. 29 8月, 2013 1 次提交
    • N
      drivers: irq-chip: irq-gic: introduce gic_cpu_if_down() · 10d9eb8a
      Nicolas Pitre 提交于
      When processors are about to hit low power states, the assertion of
      standbywfi signal, triggered by the wfi instruction, is essential to
      entering low power modes. If an IRQ is pending on the processor at the
      time wfi is issued, the wfi instruction completes and the processor
      restarts execution without asserting the standbywfi signal. Depending
      on the platform power controller HW this behaviour can be acceptable or
      not; if this behaviour must be prevented software should be provided
      with a way to disable the routing of interrupts to the core IRQ pins.
      
      On systems where raw GIC distributor interrupts are connected to the power
      controller as wake-up events (hence the power controller still senses
      IRQs and can wake up cores upon IRQ pending), the GIC CPU interface can
      be disabled on power down, so that the GIC CPU IF output is gated and wfi
      cannot complete, thereby preventing the standbywfi issue.
      
      This patch adds a simple function to the GIC driver that allows to
      disable the GIC CPU IF from power down procedures.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      [rewrote commit log]
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      10d9eb8a
  9. 30 7月, 2013 2 次提交
    • N
      ARM: bL_switcher: do not hardcode GIC IDs in the code · ed96762e
      Nicolas Pitre 提交于
      Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L
      configuration.  Let's allow for GIC IDs to be discovered upon switcher
      initialization to support other b.L configurations such as the 1+1 one,
      or 2+3 as on the VExpress TC2.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      ed96762e
    • N
      ARM: gic: add CPU migration support · 1a6b69b6
      Nicolas Pitre 提交于
      This is required by the big.LITTLE switcher code.
      
      The gic_migrate_target() changes the CPU interface mapping for the
      current CPU to redirect SGIs to the specified interface, and it also
      updates the target CPU for each interrupts to that CPU interface
      if they were targeting the current interface.  Finally, pending
      SGIs for the current CPU are forwarded to the new interface.
      
      Because Linux does not use it, the SGI source information for the
      forwarded SGIs is not preserved.  Neither is the source information
      for the SGIs sent by the current CPU to other CPUs adjusted to match
      the new CPU interface mapping.  The required registers are banked so
      only the target CPU could do it.
      Signed-off-by: NNicolas Pitre <nico@linaro.org>
      1a6b69b6
  10. 27 3月, 2013 1 次提交
  11. 12 2月, 2013 3 次提交
  12. 13 1月, 2013 3 次提交
    • R
      irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.h · 520f7bd7
      Rob Herring 提交于
      Now that we have GIC moved to drivers/irqchip and all GIC DT init for
      platforms using irqchip_init, move gic.h and update the remaining
      includes.
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Anton Vorontsov <avorontsov@mvista.com>
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: David Brown <davidb@codeaurora.org>
      Cc: Daniel Walker <dwalker@fifo99.com>
      Cc: Bryan Huntsman <bryanh@codeaurora.org>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Viresh Kumar <viresh.linux@gmail.com>
      Cc: Shiraz Hashim <shiraz.hashim@st.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Samuel Ortiz <sameo@linux.intel.com>
      520f7bd7
    • R
      ARM: use common irqchip_init for GIC init · 0529e315
      Rob Herring 提交于
      Convert all GIC DT initialization over to use common irqchip_init
      function.
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Acked-by: NShawn Guo <shawn.guo@linaro.org>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: David Brown <davidb@codeaurora.org>
      Cc: Daniel Walker <dwalker@fifo99.com>
      Cc: Bryan Huntsman <bryanh@codeaurora.org>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Viresh Kumar <viresh.linux@gmail.com>
      Cc: Shiraz Hashim <shiraz.hashim@st.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      0529e315
    • R
      ARM: remove mach .handle_irq for GIC users · 1d5cc604
      Rob Herring 提交于
      Now that the GIC initialization sets up the handle_arch_irq pointer, we
      can remove it for all machines and make it static.
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Anton Vorontsov <avorontsov@mvista.com>
      Cc: Kyungmin Park <kyungmin.park@samsung.com>
      Cc: Sascha Hauer <kernel@pengutronix.de>
      Cc: David Brown <davidb@codeaurora.org>
      Cc: Daniel Walker <dwalker@fifo99.com>
      Cc: Bryan Huntsman <bryanh@codeaurora.org>
      Acked-by: NTony Lindgren <tony@atomide.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: Magnus Damm <magnus.damm@gmail.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Shiraz Hashim <shiraz.hashim@st.com>
      Acked-by: NStephen Warren <swarren@nvidia.com>
      Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
      Acked-by: NKukjin Kim <kgene.kim@samsung.com>
      Acked-by: NShawn Guo <shawn.guo@linaro.org>
      Acked-by: NOlof Johansson <olof@lixom.net>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      1d5cc604
  13. 11 1月, 2013 2 次提交
  14. 16 2月, 2012 1 次提交
    • G
      irq_domain: Remove 'new' irq_domain in favour of the ppc one · 75294957
      Grant Likely 提交于
      This patch removes the simplistic implementation of irq_domains and enables
      the powerpc infrastructure for all irq_domain users.  The powerpc
      infrastructure includes support for complex mappings between Linux and
      hardware irq numbers, and can manage allocation of irq_descs.
      
      This patch also converts the few users of irq_domain_add()/irq_domain_del()
      to call irq_domain_add_legacy() instead.
      
      v3: Fix bug that set up too many irqs in translation range.
      v2: Fix removal of irq_alloc_descs() call in gic driver
      Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Milton Miller <miltonm@bga.com>
      Tested-by: NOlof Johansson <olof@lixom.net>
      75294957
  15. 16 11月, 2011 3 次提交
    • M
      ARM: GIC: Make MULTI_IRQ_HANDLER mandatory · 08d33b27
      Marc Zyngier 提交于
      Now that MULTI_IRQ_HANDLER is selected by all the in-tree
      GIC users, make it mandatory and remove the unused macros.
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      08d33b27
    • M
      ARM: GIC: Add global gic_handle_irq() function · 562e0027
      Marc Zyngier 提交于
      Provide the GIC code with a low level handler that can be used
      by platforms using CONFIG_MULTI_IRQ_HANDLER.
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      562e0027
    • M
      ARM: gic: allow GIC to support non-banked setups · db0d4db2
      Marc Zyngier 提交于
      The GIC support code is heavily using the fact that hardware
      implementations are exposing banked registers. Unfortunately, it
      looks like at least one GIC implementation (EXYNOS) offers both
      the distributor and the CPU interfaces at different addresses,
      depending on the CPU.
      
      This problem is solved by allowing the distributor and CPU interface
      addresses to be per-cpu variables for the platforms that require it.
      The EXYNOS code is updated not to mess with the GIC internals while
      handling interrupts, and struct gic_chip_data is back to being private.
      The DT binding for the gic is updated to allow an optional "cpu-offset"
      value, which is used to compute the various base addresses.
      
      Finally, a new config option (GIC_NON_BANKED) is used to control this
      feature, so the overhead is only present on kernels compiled with
      support for EXYNOS.
      
      Tested on Origen (EXYNOS4) and Panda (OMAP4).
      
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Thomas Abraham <thomas.abraham@linaro.org>
      Acked-by: NRob Herring <rob.herring@calxeda.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      db0d4db2
  16. 31 10月, 2011 3 次提交
  17. 23 10月, 2011 1 次提交
  18. 23 9月, 2011 1 次提交
  19. 20 7月, 2011 1 次提交
  20. 09 3月, 2011 1 次提交
    • S
      ARM: 6777/1: gic: Add hooks for architecture specific extensions · d7ed36a4
      Santosh Shilimkar 提交于
      Few architectures combine the GIC with an external interrupt
      controller. On such systems it may be necessary to update both
      the GIC registers and the external controller's registers to control
      IRQ behavior.
      
      This can be addressed in couple of possible methods.
       1. Export common GIC routines along with 'struct irq_chip gic_chip'
          and allow architectures to have custom function by override.
       2. Provide architecture specific function pointer hooks
          within GIC library and leave platforms to add the necessary
          code as part of these hooks.
      
      First one might be non-intrusive but have few shortcomings like arch
      needs to have there own custom gic library. Locks used should be
      common since it caters to same IRQs etc. Maintenance point of view
      also it leads to multiple file fixes.
      
      The second probably is cleaner and portable. It ensures that all the
      common GIC infrastructure is not touched and also provides archs to
      address their specific issue.
      
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Acked-by: NColin Cross <ccross@android.com>
      Tested-by: NColin Cross <ccross@android.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      d7ed36a4
  21. 15 12月, 2010 4 次提交
  22. 17 5月, 2009 1 次提交
  23. 03 8月, 2008 1 次提交
  24. 15 2月, 2007 1 次提交
  25. 19 8月, 2005 1 次提交