- 13 12月, 2014 3 次提交
-
-
由 Marc Zyngier 提交于
When issuing a MAPD command, one of the parameters passed to the ITS is the number of EventID bits used to index the per-device Interrupt Translation Table (ITT). Crucially, this is the number of bits *minus one*. This has two consequences: - The size of the ITT has to be a strict power of two, no matter how many different events the device is actually going to generate. - It is impossible to express an ITT with a single entry, as you would have to tell the ITS to "use zero bit from the EventID", and that clashes with "minus one" above. Fix this by allocating the ITT with the number of vectors rounded up to the next power of two, with a minimum of two entries. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Yun Wu (Abel) <wuyun.wu@huawei.com> Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Marc Zyngier 提交于
The ITS code could do a bit less in the alloc/free paths, and a bit more in the activate/deactivate methods, giving a better separation between software allocation and HW programing. Suggested-by: NWuyun Wu (Abel) <wuyun.wu@huawei.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Yun Wu (Abel) <wuyun.wu@huawei.com> Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
-
由 Marc Zyngier 提交于
Fix stupid thinko on the path freeing the interrupts, where only the first interrupt would get reset, and none of the others. This should only affect multi-MSI allocations. Reported-by: NWuyun Wu (Abel) <wuyun.wu@huawei.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Robert Richter <robert.richter@caviumnetworks.com> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
-
- 01 12月, 2014 1 次提交
-
-
由 Thomas Petazzoni 提交于
This commit adds suspend/resume support to the irqchip driver used on Armada XP platforms (amongst others). It does so by adding a set of suspend/resume syscore_ops, that will respectively save and restore the necessary registers to ensure interrupts continue to work after resume. It is worth mentioning that the affinity is lost during a suspend/resume cycle, because when a secondary CPU is brought off-line, all interrupts that are assigned to this CPU in terms of affinity gets re-assigned to a still running CPU. Therefore, right before entering suspend, all interrupts are assigned to the boot CPU. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-kernel@vger.kernel.org Link: https://lkml.kernel.org/r/1416585613-2113-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
- 27 11月, 2014 3 次提交
-
-
由 Jisheng Zhang 提交于
This patch adds in support for S2R for dw-apb-ictl irqchip driver. We can used relaxed variants in the resume hook because there's no DMA at all here, the device type memory attribute can ensure the operations order and relaxed version imply compiler barrier. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Link: https://lkml.kernel.org/r/1415773374-4629-4-git-send-email-jszhang@marvell.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Jisheng Zhang 提交于
The irq_chip_type instances have separate mask registers, so we need to enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask registers. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1415773374-4629-3-git-send-email-jszhang@marvell.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Jisheng Zhang 提交于
There's no DMA at all, the device type memory attribute can ensure the operations order and relaxed version imply compiler barrier, so we are safe to use relaxed version to improve the performance a bit. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1415773374-4629-2-git-send-email-jszhang@marvell.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
- 26 11月, 2014 16 次提交
-
-
由 Suravee Suthikulpanit 提交于
ARM GICv2m specification extends GICv2 to support MSI(-X) with a new register frame. This allows a GICv2 based system to support MSI with minimal changes. Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> [maz: converted the driver to use stacked irq domains, updated changelog] Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Yingjoe Chen 提交于
Mediatek SoCs have interrupt polarity support in sysirq which allows to invert polarity for given interrupt. Add this support using hierarchy irq domain. Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com> Link: https://lkml.kernel.org/r/1416902662-19281-3-git-send-email-yingjoe.chen@mediatek.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Yingjoe Chen 提交于
Add support to use gic as a parent for stacked irq domain. Signed-off-by: NYingjoe Chen <yingjoe.chen@mediatek.com> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416902662-19281-2-git-send-email-yingjoe.chen@mediatek.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
Get the show on the road... Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-13-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
As the ITS is always a subsystem if GICv3, its probing/init is driven by the main GICv3 code. Plug that code in (guarded by a config option). Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-12-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
Add the code that probes the ITS from the device tree, and initialize it. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-11-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
Now, the bit of code that allow us to use the ITS as a MSI controller. Both MSI and MSI-X are supported. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-10-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
The ITS has a notion of "device" that can write to it in order to generate an interrupt. Conversly, the driver maintains a per-ITS list of devices, together with their configuration information, and uses this to configure the HW. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-9-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
The interrupt translation is driven by a set of tables (device, ITT, and collection) to be in the end delivered to a CPU. Also, the redistributors rely on a couple of tables (configuration, and pending) to deliver the interrupts to the CPUs. This patch adds the required allocators for these tables. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-8-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
LPIs are the type of interrupts that are used by the ITS. Given the size of the namespace (anywhere between 16 and 32bit), interrupt IDs are allocated in chunks of 32. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-7-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
The usual methods that are used to present an irqchip to the rest of the kernel Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-6-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
The ITS is configured through a number commands that the driver issues to the HW using a memory-based circular buffer. This patch implements the subset of commands that are required for Linux. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-5-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
The basic GICv3 driver has almost no use for the redistributor (other than the basic per-CPU interrupts), but the ITS needs a lot more from them. As such, rework the set of data structures. The behaviour of the GICv3 driver is otherwise unaffected. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-4-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Marc Zyngier 提交于
In order to start supporting stacked domains, convert the GICv3 code base to the new domain hierarchy framework, which mostly amounts to supporting the new alloc/free callbacks. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-3-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Dmitry Torokhov 提交于
Return value of irq_of_parse_and_map() is unsigned int, with 0 indicating failure, so testing for negative result never works. Signed-off-by: NDmitry Torokhov <dtor@chromium.org> Acked-by: NFlorian Fainelli <f.fainelli@gmail.com> Tested-by: Kevin Cernekee <cernekee@gmail.com> Link: https://lkml.kernel.org/r/20141114221642.GA37468@dtor-wsSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
由 Dmitry Torokhov 提交于
Return value of irq_of_parse_and_map() is unsigned int, with 0 indicating failure, so testing for negative result never works. Signed-off-by: NDmitry Torokhov <dtor@chromium.org> Acked-by: NFlorian Fainelli <f.fainelli@gmail.com> Tested-by: NKevin Cernekee <cernekee@gmail.com> Link: https://lkml.kernel.org/r/20141114221614.GA37395@dtor-wsSigned-off-by: NJason Cooper <jason@lakedaemon.net>
-
- 24 11月, 2014 17 次提交
-
-
由 Andrew Bresticker 提交于
Add device-tree support for the MIPS GIC. Update the GIC irqdomain's xlate() callback to handle the three-cell specifier described in the MIPS GIC binding document. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJason Cooper <jason@lakedaemon.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8422/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
There's no reason for gic_frequency to be global any more and it certainly doesn't belong in the GIC irqchip driver, so move it to the GIC clocksource driver. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8137/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Combine the GIC clocksource driver with the GIC clockevent driver from arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate Kconfig symbol. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8132/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8133/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Use the GIC_SH_WEDGE_{SET,CLR} macros provided by mips-gic.h. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8134/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
There's no reason for the pending and masked interrupt bitmasks to be global. Just declare them on the stack in gic_get_int() since they only consume (256*2)/8 = 64 bytes. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8131/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Sort the #includes and remove those which are unnecessary. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8130/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Remove duplicate #defines and unnecessary #includes, fix parenthesization, and re-order register definitions in ascending order. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8128/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Get rid of the ugly GICREAD/GICWRITE/GICBIS macros and use proper iomem accessors instead. Since the GIC registers are not directly accessed outside of the GIC driver any more, make gic_base static and move all the GIC register manipulation macros out of gic.h, converting them to static inline functions. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8127/ Patchwork: https://patchwork.linux-mips.org/patch/8229/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Export the function gic_get_count_width to read the width of the GIC global counter from GIC_SH_CONFIG. Update the GIC clocksource driver to use this new function. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8124/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Now that all GIC interrupt routing and handling logic is in the GIC driver itself, un-export variables/functions which are no longer used outside the GIC driver. This also allows us to remove gic_compare_int and combine gic_get_int_mask with gic_get_int since these interfaces are no longer used. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7820/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7819/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
GIC edge-triggered interrupts must be acknowledged by clearing the edge detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered irq_chip with the appropriate irq_ack() callback. This also allows us to get rid of gic_irq_flags. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7818/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Instead of requiring platforms to define the correct GIC_NUM_INTRS, use the value reported in GIC_SH_CONFIG. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7817/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7816/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-
由 Andrew Bresticker 提交于
Use a simple IRQ domain for the MIPS GIC. Remove the gic_platform_init callback as it's no longer necessary for it to set the irqchip. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NJason Cooper <jason@lakedaemon.net> Reviewed-by: NQais Yousef <qais.yousef@imgtec.com> Tested-by: NQais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7811/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
-