1. 26 11月, 2014 1 次提交
  2. 22 10月, 2014 1 次提交
  3. 28 7月, 2014 1 次提交
  4. 05 2月, 2014 1 次提交
    • S
      DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs · 006e983b
      Sricharan R 提交于
      In some socs the gic can be preceded by a crossbar IP which
      routes the peripheral interrupts to the gic inputs. The peripheral
      interrupts are associated with a fixed crossbar input line and the
      crossbar routes that to one of the free gic input line.
      
      The DT entries for peripherals provides the fixed crossbar input line
      as its interrupt number and the mapping code should associate this with
      a free gic input line. This patch adds the support inside the gic irqchip
      to handle such routable irqs. The routable irqs are registered in a linear
      domain. The registered routable domain's callback should be implemented
      to get a free irq and to configure the IP to route it.
      
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
      Cc: Russell King <linux@arm.linux.org.uk>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Rajendra Nayak <rnayak@ti.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Grant Likely <grant.likely@linaro.org>
      Cc: Rob Herring <rob.herring@calxeda.com>
      Signed-off-by: NSricharan R <r.sricharan@ti.com>
      Reviewed-by: NThomas Gleixner <tglx@linutronix.de>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Acked-by: NLinus Walleij <linus.walleij@linaro.org>
      006e983b
  5. 05 12月, 2013 1 次提交
  6. 06 2月, 2013 1 次提交
  7. 11 5月, 2012 1 次提交
  8. 16 11月, 2011 1 次提交
    • M
      ARM: gic: allow GIC to support non-banked setups · db0d4db2
      Marc Zyngier 提交于
      The GIC support code is heavily using the fact that hardware
      implementations are exposing banked registers. Unfortunately, it
      looks like at least one GIC implementation (EXYNOS) offers both
      the distributor and the CPU interfaces at different addresses,
      depending on the CPU.
      
      This problem is solved by allowing the distributor and CPU interface
      addresses to be per-cpu variables for the platforms that require it.
      The EXYNOS code is updated not to mess with the GIC internals while
      handling interrupts, and struct gic_chip_data is back to being private.
      The DT binding for the gic is updated to allow an optional "cpu-offset"
      value, which is used to compute the various base addresses.
      
      Finally, a new config option (GIC_NON_BANKED) is used to control this
      feature, so the overhead is only present on kernels compiled with
      support for EXYNOS.
      
      Tested on Origen (EXYNOS4) and Panda (OMAP4).
      
      Cc: Kukjin Kim <kgene.kim@samsung.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Thomas Abraham <thomas.abraham@linaro.org>
      Acked-by: NRob Herring <rob.herring@calxeda.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      db0d4db2
  9. 31 10月, 2011 1 次提交