1. 11 2月, 2012 1 次提交
  2. 05 1月, 2012 2 次提交
  3. 28 12月, 2011 2 次提交
  4. 02 12月, 2011 7 次提交
  5. 27 11月, 2011 1 次提交
  6. 24 11月, 2011 1 次提交
  7. 21 11月, 2011 1 次提交
  8. 08 11月, 2011 1 次提交
    • S
      arm/mxs: fix mmc device adding for mach-mx28evk · e94e05ea
      Shawn Guo 提交于
      The merge commit "526b2641 Merge branch 'imx/cleanup' into imx/devel"
      left a duplicated mx28_add_mxs_mmc() call, which causes the problem
      below during boot.
      
        kobject_add_internal failed for mxs-mmc.1 with -EEXIST, don't try
        to register things with the same name in the same directory.
      
      The patch removes this leftover and also change mmc0 adding to align
      with mmc1.
      Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
      e94e05ea
  9. 25 10月, 2011 1 次提交
    • M
      ARM: i.MX28: shift frac value in _CLK_SET_RATE · 590842f9
      Matt Burtch 提交于
      Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to
      reset the clock divider for the SSP0 parent clock, in this case
      IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but
      when the new frac value is written the value isn't shifted up to write
      the correct bit-field.  This results in IO0FRAC being set to 0 and
      CPUFRAC being corrupted.
      
      This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0
      and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1.
      
      Tested on custom i.MX28 board with SSP0 SPI driver.
      Signed-off-by: NMatt Burtch <matt@grid-net.com>
      Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
      590842f9
  10. 18 10月, 2011 1 次提交
  11. 17 10月, 2011 2 次提交
  12. 14 10月, 2011 1 次提交
  13. 13 10月, 2011 1 次提交
  14. 04 10月, 2011 1 次提交
  15. 26 9月, 2011 1 次提交
  16. 20 9月, 2011 1 次提交
  17. 23 8月, 2011 8 次提交
  18. 17 8月, 2011 3 次提交
  19. 12 8月, 2011 3 次提交
  20. 20 7月, 2011 1 次提交