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  1. 05 8月, 2016 5 次提交
    • R
      sh: use common clock framework with device tree boards · 15f0c8f2
      由 Rich Felker 提交于 
      Enable common clk framework for DT-based boards and disable code that
depends on the legacy sh clk framework when common clk is enabled.
Once legacy drivers are converted over, the old code can be removed
entirely.
Signed-off-by: NRich Felker <dalias@libc.org>
      15f0c8f2
    • R
      sh: add SMP support for J2 · b4214e41
      由 Rich Felker 提交于 
      Support is hooked up via a cpu start method specified in the device
tree, and also depends on DT nodes that describe the interfaces for
performing IPI and identifying which cpu execution is taking place on.
The currently used method is a form of spin table, where secondary
cpus are unblocked by writing to a special address.
Signed-off-by: NRich Felker <dalias@libc.org>
      b4214e41
    • R
      sh: SMP support for SH2 entry.S · 4b6ef05b
      由 Rich Felker 提交于 
      The SH2 version of entry.S uses global variables, which need to be
cpu-local in order to work with SMP. For ease of access from asm,
simply use arrays indexed by cpu number, and require the availability
of an address (mmio register or properly setup per-cpu memory) from
which the current cpu's index can be read.
Signed-off-by: NRich Felker <dalias@libc.org>
      4b6ef05b
    • R
      sh: add AT_HWCAP flag for J-Core cas.l instruction · 834da197
      由 Rich Felker 提交于 
      The J-Core cpu has, as an ISA extension, an atomic compare-and-swap
instruction cas.l which applications need to use (instead the imask or
gusa atomic models, which are fundamentally limited to UP) for
synchronization in order to be compatible with SMP systems. Provide a
hwcap flag so that it's possible to do runtime selection and support
both.
Signed-off-by: NRich Felker <dalias@libc.org>
      834da197
    • R
      sh: add support for J-Core J2 processor · 5a846aba
      由 Rich Felker 提交于 
      At the CPU/ISA level, the J2 is compatible with SH-2, and thus the
changes to add J2 support build on existing SH-2 support. However, J2
does not duplicate the memory-mapped SH-2 features like the cache
interface. Instead, the cache interfaces is described in the device
tree, and new code is added to be able to access the flat device tree
at early boot before it is unflattened.

Support is also added for receiving interrupts on trap numbers in the
range 16 to 31, since the J-Core aic1 interrupt controller generates
these traps. This range was unused but nominally for hardware
exceptions on SH-2, and a few values in this range were used for
exceptions on SH-2A, but SH-2A has its own version of the relevant
code.

No individual cpu subtypes are added for J2 since the intent moving
forward is to represent SoCs with device tree rather than as
hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item
exists only to fit into the existing cpu selection mechanism until it
is overhauled.
Signed-off-by: NRich Felker <dalias@libc.org>
      5a846aba
  3. 31 7月, 2016 1 次提交
    • R
      sh: disable aliased page logic on NOMMU models · 57155c65
      由 Rich Felker 提交于 
      SH3/4 (with MMU) have a virtually indexed cache, requiring explicit
work to avoid consistency problems arising from having the same
physical address range cached in multiple cache lines. This is
unneeded for the NOMMU case, and some of the resulting code paths
(kmap_coherent) don't work. SH2 only avoided this problem by having a
4-way associative cache with way size equal to the page size (4k),
yielding no cache index bits outside of the page offset and thus no
aliases.
Signed-off-by: NRich Felker <dalias@libc.org>
      57155c65
  5. 30 3月, 2016 1 次提交
  7. 18 3月, 2016 1 次提交
    • R
      sh: provide unified syscall trap compatible with all SH models · 3623d138
      由 Rich Felker 提交于 
      Historically SH-2 Linux (and originally uClinux) used a syscall
calling convention incompatible with the established SH-3/4 Linux ABI.
This choice was made because the trap range used by the existing ABI,
0x10-0x17, overlaps with the hardware exception/interrupt trap range
reserved by SH-2, and in particular, with the SH-2A divide-by-zero and
division-overflow exceptions.

Despite the documented syscall convention using the low bits of the
trap number to signal the number of arguments the kernel should
expect, no version of the kernel has ever used this information, nor
is it useful; all of the registers need to be saved anyway. Therefore,
it is possible to pick a new trap number, 0x1f, that is both supported
by all existing SH-3/4 kernels and unassigned as a hardware trap in
the SH-2 range. This makes it possible to produce SH-2 application
binaries that are forwards-compatible with running on SH-3/4 kernels
and to treat SH as a unified platform with varying ISA support levels
rather than multiple gratuitously-incompatible platforms.

This patch adjusts the range checking SH-2 and SH-2A kernels make for
the syscall trap to accept the range 0x1f-0x2f rather than just
0x20-0x2f. As a result, trap 0x1f now acts as a syscall for all SH
models.
Signed-off-by: NRich Felker <dalias@libc.org>
      3623d138
  9. 17 12月, 2015 3 次提交
  11. 07 11月, 2015 1 次提交
  13. 06 8月, 2015 1 次提交
  15. 06 7月, 2015 1 次提交
  17. 06 5月, 2015 1 次提交
  19. 13 11月, 2014 1 次提交
    • D
      cpuidle: Invert CPUIDLE_FLAG_TIME_VALID logic · b82b6cca
      由 Daniel Lezcano 提交于 
      The only place where the time is invalid is when the ACPI_CSTATE_FFH entry
method is not set. Otherwise for all the drivers, the time can be correctly
measured.

Instead of duplicating the CPUIDLE_FLAG_TIME_VALID flag in all the drivers
for all the states, just invert the logic by replacing it by the flag
CPUIDLE_FLAG_TIME_INVALID, hence we can set this flag only for the acpi idle
driver, remove the former flag from all the drivers and invert the logic with
this flag in the different governor.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      b82b6cca
  21. 30 10月, 2014 1 次提交
  23. 07 8月, 2014 1 次提交
  25. 15 7月, 2014 1 次提交
  27. 11 5月, 2014 3 次提交
  29. 04 4月, 2014 1 次提交
  31. 04 3月, 2014 1 次提交
  33. 24 12月, 2013 3 次提交
  35. 13 11月, 2013 1 次提交
  37. 23 8月, 2013 1 次提交
  39. 21 8月, 2013 2 次提交
  41. 12 8月, 2013 1 次提交
  43. 15 7月, 2013 1 次提交
    • P
      sh: delete __cpuinit usage from all sh files · 4603f53a
      由 Paul Gortmaker 提交于 
      The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit  -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings.  In any case, they are temporary and harmless.

This removes all the arch/sh uses of the __cpuinit macros from
all C files.  Currently sh does not have any __CPUINIT used in
assembly files.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      4603f53a
  45. 08 6月, 2013 3 次提交
  47. 24 4月, 2013 1 次提交
  49. 23 4月, 2013 1 次提交
  51. 22 4月, 2013 2 次提交