1. 10 8月, 2016 2 次提交
    • B
      powerpc/32: Fix crash during static key init · 97f6e0cc
      Benjamin Herrenschmidt 提交于
      We cannot do those initializations from apply_feature_fixups() as
      this function runs in a very restricted environment on 32-bit where
      the kernel isn't running at its linked address and the PTRRELOC()
      macro must be used for any global accesss.
      
      Instead, split them into a separtate steup_feature_keys() function
      which is called in a more suitable spot on ppc32.
      
      Fixes: 309b315b ("powerpc: Call jump_label_init() in apply_feature_fixups()")
      Reported-and-tested-by: NChristian Kujau <lists@nerdbynature.de>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      97f6e0cc
    • C
      powerpc/ptrace: Fix coredump since ptrace TM changes · c7a318ba
      Cyril Bur 提交于
      Commit 8d460f61 ("powerpc/process: Add the function
      flush_tmregs_to_thread") added flush_tmregs_to_thread() and included
      the assumption that it would only be called for a task which is not
      current.
      
      Although this is correct for ptrace, when generating a core dump, some
      of the routines which call flush_tmregs_to_thread() are called. This
      leads to a WARNing such as:
      
        Not expecting ptrace on self: TM regs may be incorrect
        ------------[ cut here ]------------
        WARNING: CPU: 123 PID: 7727 at arch/powerpc/kernel/process.c:1088 flush_tmregs_to_thread+0x78/0x80
        CPU: 123 PID: 7727 Comm: libvirtd Not tainted 4.8.0-rc1-gcc6x-g61e8a0d5 #1
        task: c000000fe631b600 task.stack: c000000fe63b0000
        NIP: c00000000001a1a8 LR: c00000000001a1a4 CTR: c000000000717780
        REGS: c000000fe63b3420 TRAP: 0700   Not tainted  (4.8.0-rc1-gcc6x-g61e8a0d5)
        MSR: 900000010282b033 <SF,HV,VEC,VSX,EE,FP,ME,IR,DR,RI,LE,TM[E]>  CR: 28004222  XER: 20000000
        ...
        NIP [c00000000001a1a8] flush_tmregs_to_thread+0x78/0x80
        LR [c00000000001a1a4] flush_tmregs_to_thread+0x74/0x80
        Call Trace:
         flush_tmregs_to_thread+0x74/0x80 (unreliable)
         vsr_get+0x64/0x1a0
         elf_core_dump+0x604/0x1430
         do_coredump+0x5fc/0x1200
         get_signal+0x398/0x740
         do_signal+0x54/0x2b0
         do_notify_resume+0x98/0xb0
         ret_from_except_lite+0x70/0x74
      
      So fix flush_tmregs_to_thread() to detect the case where it is called on
      current, and a transaction is active, and in that case flush the TM regs
      to the thread_struct.
      
      This patch also moves flush_tmregs_to_thread() into ptrace.c as it is
      only called from that file.
      
      Fixes: 8d460f61 ("powerpc/process: Add the function flush_tmregs_to_thread")
      Signed-off-by: NCyril Bur <cyrilbur@gmail.com>
      [mpe: Flesh out change log]
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      c7a318ba
  2. 09 8月, 2016 2 次提交
    • M
      powerpc/powernv: Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h · 98d8821a
      Mahesh Salgaonkar 提交于
      Move IDLE_STATE_ENTER_SEQ macro to cpuidle.h so that MCE handler changes
      in subsequent patch can use it.
      
      No functionality change.
      Signed-off-by: NMahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      98d8821a
    • B
      powerpc/xics: Properly set Edge/Level type and enable resend · 880a3d6a
      Benjamin Herrenschmidt 提交于
      This sets the type of the interrupt appropriately. We set it as follow:
      
       - If not mapped from the device-tree, we use edge. This is the case
      of the virtual interrupts and PCI MSIs for example.
      
       - If mapped from the device-tree and #interrupt-cells is 2 (PAPR
      compliant), we use the second cell to set the appropriate type
      
       - If mapped from the device-tree and #interrupt-cells is 1 (current
      OPAL on P8 does that), we assume level sensitive since those are
      typically going to be the PSI LSIs which are level sensitive.
      
      Additionally, we mark the interrupts requested via the opal_interrupts
      property all level. This is a bit fishy but the best we can do until we
      fix OPAL to properly expose them with a complete descriptor. It is also
      correct for the current HW anyway as OPAL interrupts are currently PCI
      error and PSI interrupts which are level.
      
      Finally now that edge interrupts are properly identified, we can enable
      CONFIG_HARDIRQS_SW_RESEND which will make the core re-send them if
      they occur while masked, which some drivers rely upon.
      
      This fixes issues with lost interrupts on some Mellanox adapters.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      880a3d6a
  3. 04 8月, 2016 3 次提交
  4. 03 8月, 2016 2 次提交
  5. 01 8月, 2016 30 次提交
  6. 27 7月, 2016 1 次提交