- 23 6月, 2013 2 次提交
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由 Tushar Behera 提交于
cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. Clock alias modifications for EXYNOS4 specific clocks are as below. Alias for clock 'arm_clk' is 'armclk'. Alias for clock 'mout_apll' is 'mout_apll'. Alias for clock 'mout_core' is 'moutcore'. For EXYNOS4210, alias for clock 'sclk_mpll' is 'mout_mpll'. For EXYNOS4412, alias for clock 'mout_mpll_user_c' is 'mout_mpll'. Some of the clock aliases are newly defined and some are fixed up. While at it, also modify the debug messages to print the clock values appropriately. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
Cpufreq driver for some Samsung platforms have not yet been designed as a platform driver, thereby they can only access clocks with an alias name. For EXYNOS4210, one such clock also requires a flag to be set, hence there is a need to create another macro that can handle both flag and alias. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 21 6月, 2013 1 次提交
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由 Heiko Stübner 提交于
This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 20 6月, 2013 4 次提交
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由 Linus Walleij 提交于
The Nomadik clock implementation was a stub just using fixed clocks. This implements the clocks properly instead of relying on them all being on at boot and leaving them all on. The PLLs are on the top locking to the main chrystal oscillator, then the HCLK for the peripherals are below PLL2. The gated clocks are implemented with zero cells and given the clock ID as a property of each node, so every gate need to have its own node in the device tree. This is because the gate registers contain both HCLK gates and PCLK gates, where the latter has HCLK as parent. As can be seen from the register layout, this is a complete mixup, which means all these gates need their own node to properly model parent/child relations for PCLKs apart from the HCLKs. This driver also adds a helpful debugfs file to inspect the hardware state of the clock gates. This is the end result in <debugfs>/clk/clk_summary after applying a proper device tree: ulpiclk 0 0 60000000 mxtal 3 3 19200000 pll2 1 1 864000000 clk48 3 3 48000000 rngcclk 1 1 48000000 usbmclk 0 0 48000000 mshcclk 0 0 48000000 mspclk3 0 0 48000000 x3dclk 0 0 48000000 skeclk 0 0 48000000 owmclk 0 0 48000000 mspclk2 0 0 48000000 mspclk1 0 0 48000000 uart2clk 0 0 48000000 ipbmcclk 0 0 48000000 ipi2cclk 0 0 48000000 usbclk 0 0 48000000 mspclk0 0 0 48000000 uart1clk 1 2 48000000 i2c1clk 0 0 48000000 i2c0clk 0 0 48000000 sdiclk 1 1 48000000 uart0clk 0 0 48000000 sspiclk 0 0 48000000 irdaclk 0 0 48000000 clk72 0 0 72000000 difclk 0 0 72000000 clcdclk 0 0 72000000 clk216 0 0 216000000 hsiclkrx 0 0 216000000 clk108 0 0 108000000 hsiclktx 0 0 108000000 clk27 0 0 27000000 pll1 1 1 264000000 hclk 3 3 264000000 hclkrng 1 1 264000000 hclkusbm 0 0 264000000 hclkcryp 0 0 264000000 hclkhash 0 0 264000000 hclk3d 0 0 264000000 hclkhpi 0 0 264000000 hclksva 0 0 264000000 hclksaa 0 0 264000000 hclkdif 0 0 264000000 hclkusb 0 0 264000000 hclkclcd 0 0 264000000 hclkdma1 0 0 264000000 hclksdram 0 0 264000000 hclksmc 1 1 264000000 hclkdma0 0 0 264000000 pclk 7 9 264000000 pclkmsp3 0 0 264000000 pclkmshc 0 0 264000000 pclkhsem 0 0 264000000 pclkske 0 0 264000000 pclkowm 0 0 264000000 pclkmsp2 0 0 264000000 pclkmsp1 0 0 264000000 pclkuart2 0 0 264000000 pclkxti 0 0 264000000 pclkhsi 0 0 264000000 pclkmsp0 0 0 264000000 pclkuart1 1 1 264000000 pclki2c1 0 0 264000000 pclki2c0 0 0 264000000 pclksdi 1 1 264000000 pclkuart0 1 1 264000000 pclkssp 0 0 264000000 pclkirda 0 0 264000000 timclk 1 1 2400000 Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Pawel Moll 提交于
The new arm64 architecture has no idea of platform or machine, so it doesn't have to define ARCH_VEXPRESS configuration option at all. To allow user to select the drivers at all, make it depend on ARM64 as well. Signed-off-by: NPawel Moll <pawel.moll@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Pawel Moll 提交于
Previously all the clocks were reported as "osc". Now it will be something like "/dcc/osc@0". Signed-off-by: NPawel Moll <pawel.moll@arm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Arnd Bergmann 提交于
I got a build error today that made me realize that it is not possible to build a kernel for a SiRF platform without enabling CONFIG_PRIMA2, since a lot of common code depends on CONFIG_PRIMA2. This fixes all occurences that appear like common SiRF code. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NWolfram Sang <wsa@the-dreams.de> Acked-by: NMark Brown <broonie@linaro.org> Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: NBarry Song <Baohua.Song@csr.com> Acked-by: NMike Turquette <mturquette@linaro.org>
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- 19 6月, 2013 7 次提交
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由 Mika Westerberg 提交于
Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with few differences. Peripherals are clocked with different speeds (typically lower) and the clock is not always gated. To support this we add possibility to share a common fixed rate clock and make clock gating optional. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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由 Chander Kashyap 提交于
The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Paul Walmsley 提交于
Add DFLL DVCO reset line control functions to the CAR IP block driver. The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and saving hours of debugging time. Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Paul Walmsley 提交于
Add the input clocks needed by the DFLL IP blocks. Initialize them to 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source. This patch is a collaboration with Peter De Schrijver <pdeschrijver@nvidia.com>. Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout issues. Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: NAndrew Chew <achew@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Padmavathi Venna 提交于
This patch adds enum entries for div_i2s1 and div_i2s2 which are required for i2s1 and i2s2 controllers. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Padmavathi Venna 提交于
Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: NPadmavathi Venna <padma.v@samsung.com> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Paul Walmsley 提交于
Add clock functions to initialize, enable, and disable the FCPU clock shapers, based on the FCPU voltage rail state. These will be used by the DFLL clocksource driver code. This version of the patch contains a fix for a problem noticed by Andrew Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were incorrectly defined. Based on code originally written by Aleksandr Frid <afrid@nvidia.com>. Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com> Cc: Andrew Chew <achew@nvidia.com> Reviewed-by: NAndrew Chew <achew@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 17 6月, 2013 5 次提交
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由 Linus Walleij 提交于
This converts the last of the U300 clocks to being probed from the device tree. Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This moves the slow, fast, AHB bridge and "rest" clocks on the U300 system controller over to registration from the device tree. Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
This converts the fixed and fixed-factor clocks in the U300 platform to register themselves from the device tree. Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Get rid of the <mach/syscon.h> header as a prerequisite for multiplatform support. Do this by pushing the registers down to their respective drivers and deleting the unused remainder. Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Jay Agarwal 提交于
Registering pciex as peripheral clock instead of fixed clock as tegra_perih_reset_assert(deassert) api of this clock api gives warning and ultimately does not succeed to assert(deassert) Signed-off-by: NJay Agarwal <jagarwal@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 16 6月, 2013 4 次提交
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由 Haojian Zhuang 提交于
In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Haojian Zhuang 提交于
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Haojian Zhuang 提交于
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Soren Brinkmann 提交于
A clock's notifier count only reflects notifiers which are registered directly for that clock. A reparent operation though affects the whole subtree because of a potential rate change. When issuing the pre rate change notifications only the notifier count for the clock to be changed is considered and notifiers for subclocks may never be called. Resulting in clocks in the subtree which have registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE notification, without a PRE_RATE_CHANGE_NOTIFICATION. Therefore always traverse the whole subtree when issueing pre rate change notifications during a reparent operation. Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 12 6月, 2013 17 次提交
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由 Tushar Behera 提交于
Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
debugfs uses the rate field directly. However this ignores the CLK_GET_RATE_NOCACHE flag. Call clk_get_rate() instead. Tested-by: NMark Zhang <markz@nvidia.com> Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE is set. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
Define override bits for Tegra30 PLLM. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
Define override bits for Tegra114 PLLM. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge conflict]
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由 Peter De Schrijver 提交于
PLLM can have override bits in the PMC. Describe those in the PLL parameters. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
Use the correct parents for sclk according to the TRM. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
The PLLRE flags weren't set correctly. Fixed in this patch. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
The m,n,p fields don't have the same bit offset and width across all PLLs. This patch allows SoC specific files to indicate the offset and width. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Peter De Schrijver 提交于
The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Dinh Nguyen 提交于
Add support to gate the clocks that directly feed peripherals. For clocks with multiple parents, add the ability to determine the correct parent, and also set parents. Also add support to calculate and set the clocks' rate. Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Reviewed-by: NPavel Machek <pavel@denx.de> Acked-by: NMike Turquette <mturquette@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> CC: <linux@arm.linux.org.uk> v4: - Add Acked-by: Mike Turquette v3: - Addressed comments from Pavel v2: - Fix space/indent errors - Add streq for strcmp == 0 Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Peter De Schrijver 提交于
The pllc and pllxc code weren't always using the correct pdiv_map to map between the post divider value and the hw p field. This could result in illegal values being programmed in the hw. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Arnd Bergmann 提交于
This patch is required to be able to disable spear320 support after the spear320_clk_init() prototype changed for the real function but not for the dummy. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Doug Anderson 提交于
The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: NDoug Anderson <dianders@chromium.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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