This moves out the FPGA IRQ controller setup code to its own file, in
preparation for switching off of IRL mode and having it provide its own
irq_chip.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This does a bit of refactoring of the FPGA management code. The primary
FPGA initialization is moved out to its own file in preparation for
implementing some of the more complex capabilities, a complete set of
register definitions is provided, and all of the existing users in the
board code are moved over to use the new interface instead of setting up
overlapping mappings. This also corrects the FPGA size, which previously
was chomped off at the SDIF control register.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This uses the mode pins exposed through the FPGA to work out whether
we're driven from EXTAL or not and does the appropriate setup and
propagation through the clock framework.

This will also -EINVAL out for anyone adding in their own oscillators,
forcing proper configuration with the clock framework instead of
proceeding on with bogus clock values.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This wires up the mode pins support on the SDK7786. The pins are
standard SH7786 pins, and all are fixed in software. Needed for the
clock framework, PCIe, and so forth.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Hand off the user LEDs to the heartbeat driver.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This stubs in some preliminary board support for the RTE SDK7786.

This is quite stunted at the moment, and primarily builds on top of the
system FPGA. FPGA IRQs are handled via CPU IRL masking for simplicity,
with initial peripheral support restricted to the debug ethernet.
Signed-off-by: NMatt Fleming <matt@console-pimps.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>