This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53).
Exynos5433 supports PSCI (Power State Coordination Interface) v0.1.

This patch includes following Device Tree nodes to support Exynos5433 SoC:
1. Octa cores for big.LITTLE architecture
- Cortex-A53 LITTLE Quad-core
- Cortex-A57 big Quad-core
- Supporting PSCI v0.1

2. Clock controller nodes
- CMU_TOP   : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
- CMU_CPIF  : clocks for LLI (Low Latency Interface)
- CMU_MIF   : clocks for DRAM Memory Controller
- CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS
- CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC
- CMU_FSYS  : clocks for USB/UFS/SDMMC/TSI/PDMA
- CMU_G2D   : clocks for G2D/MDMA
- CMU_DISP  : clocks for DECON/HDMI/DSIM/MIXER
- CMU_AUD   : clocks for Cortex-A5/BUS/AUDIO
- CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses
- CMU_G3D   : clocks for 3D Graphics Engine
- CMU_GSCL  : clocks for GSCALER
- CMU_APOLLO: clocks for Cortex-A53 Quad-core processor.
- CMU_ATLAS : clocks for Cortex-A57 Quad-core processor,
              CoreSight and L2 cache controller.
- CMU_MSCL  : clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- CMU_MFC   : clocks for MFC (Multi-Format Codec) IP.
- CMU_HEVC  : clocks for HEVC(High Efficiency Video Codec) decoder IP.
- CMU_ISP   : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
- CMU_CAM0  : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
- CMU_CAM1  : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.

3. Pinctrl nodes for GPIO
- alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad

4. Timers
- ARM architecture timer (armv8-timer)
- MCT (Multi Core Timer) timer

5. Interrupt controller (GIC-400)

6. BUS devices
- HS-I2C (High-Speed I2C) device
- SPI (Serial Peripheral Interface) device

7. Sound devices
- I2S bus
- LPASS (Low Power Audio Subsystem)

8. Power management devices
- CPUFREQ for for Cortex-A53/A57
- TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP

9. Display controller devices
- DECON (Display and enhancement controller) for panel output
- DSI (Display Serial Interface)
- MIC (Mobile Image Compressor)

10. USB
- USB 3.0 DRD (Dual Role Device) controller
- USB 3.0 Host controller

11. Storage devices
- MSHC (Mobile Storage Host Controller)

12. Misc devices
- UART devices
- ADC (Analog Digital Converter)
- PWM (Pulse Width Modulation)
- ADMA (Advanced DMA) and PDMA (Peripheral DMA)
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NSeung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: NInki Dae <inki.dae@samsung.com>
Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NJaewon Kim <jaewon02.kim@samsung.com>
Signed-off-by: NHyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: NInha Song <ideal.song@samsung.com>
Signed-off-by: NIngi kim <ingi2.kim@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NAndi Shyti <andi.shyti@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>

This patch adds the L2 cache topology for berlin4ct which has 1MB L2
cache.

[Sebastian: rename cache node from "l2-cache" to "cache"]
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

After commit f29a72c2 ("watchdog: dw_wdt: Convert to use watchdog
infrastructure"), the dw_wdt driver can support multiple variants, so
unconditionally enable all dw_wdt nodes now.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Commit ac82d127 ("arm64: perf: add Cortex-A53 support") adds the
cortex A53 PMU support, thus instead of using the generic armv8-pmuv3
compatibility use the more specific Cortex A53 compatibility.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Enable throttle function for SOC_THERM.
Set "hot" trips for cpu and gpu thermal zones, which
can trigger the SOC_THERM hardware throttle.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Set general "critical" trip temperatures for cpu, gpu, mem and pllx
thermal zones on Tegra210, these trips can trigger shut down or reset.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Adds soctherm node for Tegra210, and add cpu,
gpu, mem, pllx as thermal-zones. Set critical
trip temperatures for them.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Enable throttle function for SOC_THERM.
Set "hot" trips for cpu and gpu thermal zones, which
can trigger the SOC_THERM hardware throttle.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Set general "critical" trip temperatures for cpu, gpu, mem and pllx
thermal zones on Tegra132, these trips can trigger shut down or reset.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

The Tegra132 has the specific settings for soctherm,
so change to use campatible "nvidia,tegra132-soctherm" for it.
And adds cpu, gpu, mem and pllx thermal zones.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Add device tree support for ZX296718 SoC and evaluation board based
on it.  Also document new values.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
[khilman: rename vbus node to match P200 schematics]
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add DT nodes to enable APM X-Gene 2 CPU clocks.

[dhdang: changelog]
Signed-off-by: NHoan Tran <hotran@apm.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>

This patch adds DT node to enable hwmon driver for APM X-Gene SoC.
Signed-off-by: NHoan Tran <hotran@apm.com>
Acked-by: NGuenter Roeck <linux@roeck-us.net>

On X-Gene v1 and X-Gene v2, PCIe legacy interrupt
should be configured as level-active high.
Signed-off-by: NDuc Dang <dhdang@apm.com>

This patch adds APM X-Gene v2 SoC PMU DTS entries.
Signed-off-by: NDuc Dang <dhdang@apm.com>
Cc: Tai Nguyen <ttnguyen@apm.com>

This patch adds APM X-Gene SoC PMU DTS entries.
Signed-off-by: NTai Nguyen <ttnguyen@apm.com>

The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: NDuc Dang <dhdang@apm.com>
Acked-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the nodes for the dwc2 USB controller and the related USB PHYs.
Currently we force usb0 to host mode because OTG is currently not
working in our PHY driver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add nodes for i2c bus on gxbb based platforms.
On the OdroidC2 (I2C A) and P200 (I2C B), the pull-up resistor are
present directly on the board. This indicates that these pins are
dedicated to i2c.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This is used to configure the pins of the sd_emmc_a controller to
which an SDIO module is connected (when available).
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Amlogic reference driver uses the "mc_val" devicetree property to
configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic
values for this configuration.
According to the datasheet the PRG_ETHERNET_ADDR0 register is at address
0xc8834108. However, the reference driver uses 0xc8834540 instead.
According to my tests, the value from the reference driver is correct.

No changes are required to the board dts files because the only
required configuration option is the phy-mode, which had to be
configured correctly before as well.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NJérôme Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

All of these have a Realtek Gbit RGMII PHY.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This commit adds a reference to the appropriate MSI controller in the
description of the PCIe controllers on Marvel Armada 7K and 8K
platforms.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The ../../../arm... style cross-references added by commit 9d56c22a
("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.") do not work in the
context of the split device-tree repository[0] (where the directory
structure differs). As with commit 8ee57b81 ("ARM64: dts: vexpress: Use
a symlink to vexpress-v2m-rs1.dtsi from arch=arm") use symlinks instead.

[0] https://git.kernel.org/cgit/linux/kernel/git/devicetree/devicetree-rebasing.git/Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rpi-kernel@lists.infradead.org
Cc: arm@kernel.org
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls2080a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: NLiu Gang <Gang.Liu@nxp.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add GPIO device nodes to the DT of the r8a7796 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

Adds pin control for SCIF2.
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds pinctrl device node for R8A7796 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This supports GPIO leds on H3ULCB board
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This supports SSI sound for H3ULCB board.
SSI DMA mode used. CS2000 used as AUDIO_CLK_B.
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This supports SDHI0 on H3ULCB board SD card slot
Signed-off-by: NVladimir Barinov <vladimir.barinov@cogentembedded.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>