1. 31 3月, 2018 1 次提交
  2. 29 3月, 2018 2 次提交
  3. 24 3月, 2018 3 次提交
  4. 22 3月, 2018 1 次提交
  5. 21 3月, 2018 1 次提交
  6. 20 3月, 2018 2 次提交
    • K
      drm/i915/icl: Update subslice define for ICL 11 · d3d57927
      Kelvin Gardiner 提交于
      ICL 11 has a greater number of maximum subslices. This patch
      reflects this.
      
      v2: GEN11 updates to MCR_SELECTOR (Oscar)
      v3: Copypasta error in the new defines (Lionel)
      
      Bspec: 21139
      BSpec: 21108
      Signed-off-by: NKelvin Gardiner <kelvin.gardiner@intel.com>
      Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> (v1)
      Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v1)
      Signed-off-by: NOscar Mateo <oscar.mateo@intel.com>
      Reviewed-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-3-mika.kuoppala@linux.intel.comSigned-off-by: NMika Kuoppala <mika.kuoppala@linux.intel.com>
      d3d57927
    • O
      drm/i915/icl: Check for fused-off VDBOX and VEBOX instances · 26376a7e
      Oscar Mateo 提交于
      In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
      Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
      each VDBOX and VEBOX has its own power well, which only exist if the
      related engine exists in the HW.
      
      Unfortunately, we have a Catch-22 situation going on: we need the blitter
      forcewake to read the register with the fuse info, but we cannot initialize
      the forcewake domains without knowin about the engines present in the HW.
      We workaround this problem by allowing the initialization of all forcewake
      domains and then pruning the fused off ones, as per the fuse information.
      
      Bspec: 20680
      
      v2: We were shifting incorrectly for vebox disable (Vinay)
      
      v3: Assert mmio is ready and warn if we have attempted to initialize
          forcewake for fused-off engines (Paulo)
      
      v4:
        - Use INTEL_GEN in new code (Tvrtko)
        - Shorter local variable (Tvrtko, Michal)
        - Keep "if (!...) continue" style (Tvrtko)
        - No unnecessary BUG_ON (Tvrtko)
        - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
        - Use I915_READ_FW (Michal)
        - Use I915_MAX_VCS/VECS macros (Michal)
      
      v5: Rebased by Rodrigo fixing conflicts on top of:
          "drm/i915: Simplify intel_engines_init"
      
      v6: Fix v5. Remove info->num_rings. (by Oscar)
      
      v7: Rebase (Rodrigo).
      
      v8:
        - s/intel_device_info_fused_off_engines/
          intel_device_info_init_mmio (Chris)
        - Make vdbox_disable & vebox_disable local variables (Chris)
      
      v9:
        - Move function declaration to intel_device_info.h (Michal)
        - Missing indent in bit fields definitions (Michal)
        - When RC6 is enabled by BIOS, the fuse register cannot be read until
          the blitter powerwell is awake. Shuffle where the fuse is read, prune
          the forcewake domains after the fact and change the commit message
          accordingly (Vinay, Sagar, Chris).
      
      v10:
        - Improved commit message (Sagar)
        - New line in header file (Sagar)
        - Specify the message in fw_domain_reset applies to ICL+ (Sagar)
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NOscar Mateo <oscar.mateo@intel.com>
      Reviewed-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180316121456.11577-1-mika.kuoppala@linux.intel.com
      [Mika: soothe checkpatch on commit msg]
      Signed-off-by: NMika Kuoppala <mika.kuoppala@linux.intel.com>
      26376a7e
  7. 17 3月, 2018 1 次提交
  8. 15 3月, 2018 3 次提交
  9. 14 3月, 2018 2 次提交
  10. 13 3月, 2018 1 次提交
    • R
      drm/i915/psr: Display WA 0884 applied broadly for more HW tracking. · caa1fd66
      Rodrigo Vivi 提交于
      WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
      the CPU host modify writes may not get updated on the Display
      as expected.
      WA: Write 0x00000000 to CUR_SURFLIVE_A with every CPU
      host modify write to trigger PSR exit."
      
      We can also find on spec other cases where they describe
      bogus writes to cursor registers to force PSR exit with
      HW tracking. And it was confirmed by HW engineers that
      this Wa can be safely applied for any frontbuffer activity.
      
      So let's use this more and more here instead of forcibly
      disable and re-enable PSR everytime that we have a simple
      reliable flush case.
      
      Other commits improve the fbcon/fbdev use a lot, but this
      approach is the only when where we can get a fully reliable
      console with no slowness or missed frames and PSR still
      enabled and active.
      
      v2: - Rebase on drm-tip
          - (DK) Add a comment to explain that WA
          tells about writing 0 to CUR_SURFLIVE_A but we write to
          CUR_SURFLIVE(pipe).
      v3: Wa doesn't work on PSR2.
      
      Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Reviewed-by: NDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20180309005218.26772-1-rodrigo.vivi@intel.com
      caa1fd66
  11. 08 3月, 2018 1 次提交
  12. 07 3月, 2018 3 次提交
  13. 01 3月, 2018 1 次提交
  14. 23 2月, 2018 1 次提交
  15. 22 2月, 2018 1 次提交
  16. 16 2月, 2018 1 次提交
  17. 13 2月, 2018 4 次提交
  18. 06 2月, 2018 1 次提交
  19. 01 2月, 2018 4 次提交
  20. 31 1月, 2018 5 次提交
  21. 25 1月, 2018 1 次提交