This groups USB PWEN and OVC pins together on R8A7791 SoC,
the same way it's done on R8A7790, since both are needed
for a USB device.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/).
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The arrays are never modified, declare them as const.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The arrays are never modified, declare them as const.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The arrays are never modified, make them const.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The enum_ids and var_field_width fields of struct pinmux_data_reg and
pinmux_cfg_reg are initialized using compound literals. Cast them to
const to store them in .rodata.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Set g->out_bit bit for gpio output high, clear g->out_bit bit for gpio output
low.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Replace the clk_prepare and clk_enable calls by a single
clk_prepare_enable call.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

clk_unprepare shall be called before clk_disable.
Fix the issue by replacing the clk_unprepare and clk_disable calls by a
single clk_disable_unprepare call.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This commit adds slew-rate and input-enable/disable support for pinconf
-generic.
Signed-off-by: NSherman Yin <syin@broadcom.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use the more specific form 8974 for the compatible to reduce the
risk of future mishaps.
Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Make the bitmaps part of the msm_pinctrl allocation instead of
separately allocating them.
Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add GPIOLIB and OF as dependencies for PINCTRL_MSM8X74, to fix
build errors from i386-randconfig.
Also add help text and make the entries tristate, while touching
these entries.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@sonymobile.com>
[Rebased on top of pin control development branch]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This allows to get the pin configuration by using debugfs. On my system:
 # cat /sys/kernel/debug/pinctrl/pinctrl.3/pinconf-pins
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a driver for the Tegra124 pinmux, and required
parameterization data for Tegra124.

The driver uses the common Tegra pincontrol driver utility
functions to implement the majority of the driver.

This driver is not compatible with the earlier NVIDIA's SoCs,
hence add new compatibile as "nvidia,tegra124-pinmux".

Originally written by Ashwini Gguhe.
Thierry:
 - Cleanups in patches.
ldewangan:
 - Fix some entries for groups.
 - Fix MUX enums and group sequence.
Signed-off-by: NAshwini Ghuge <aghuge@nvidia.com>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
CC: Thierry Reding <treding@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This device tree binding document describes the Tegra124 pincontrol
DT bindings. This document lists all valid properties, names, mux
options of Tegra124 pins.

Changes from V1:
- Referred the dt-binding header file on describing the nodes.

Changes from V2:
- Rewording reg properties.
- drop drv_type as it is not applicable.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

On non-DT platforms IRQ controllers associated with the GPIOs have a
fixed IRQ base value known at compile time. The sh-pfc driver translates
GPIO number to IRQ numbers using a hardcoded table. This mechanism
breaks on DT platforms, as the IRQ base values are dynamic in that case.

Fix this by specifying IRQs associated with GPIOs in IRQ resources,
populated automatically from the device tree. When IRQ resources are
specified the driver requires one IRQ resource per GPIO able to generate
an interrupt, and uses the translation table to compute the IRQ resource
offset instead of the IRQ number.

Cc: devicetree@vger.kernel.org
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There's more than one window, name the field windows.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This makes catching duplicate entries easier. Merge the two IRQ9 entries
found after sorting.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The external IRQ15 input multiplexed on GPIO 0 is missing. Add it.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ
lists.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Some indices take positive values only, make them unsigned.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

ops->pin_config_get() is only used in one specific path that will only be taken
for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf
by using debugfs.

By removing the check in pinconf_check_ops(), let's stop pressuring people to
write a pin_config_get() function that will never be used and so will probably
never be tested.

Removing the check in pinconf_pins_show() allows driver to not implement
pin_config_get() but still get a dump of the pinconf in debugfs by implementing
pin_config_dbg_show().

Finally, not implementing pin_config_get() now results in returning -ENOTSUPP
instead of -EINVAL. While this doesn't have any real impact for now, this feels
more right.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When passing a not initialized config parameter, at91_pinconf_get() would return
a bogus value. Fix that by initializing it to zero before using it.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We had a compilation failure on x86_64 due to missing OF support
as this was an implicit dependency. Add an explicit dependency
on OF and OF_IRQ on the SoC driver.

Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

There are VIN2 and VIN3 channels available on the R8A7790 SoC.
VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit.
Add both here, covering all possible data pin configurations.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

Both VIN0 and VIN1 channels support identical input interfaces.
Add missing VIN1 pins here and organize them in the same pin
groups as VIN0.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This reorganizes and renames VIN0 data pin groups to cover
all possible configurations. There's total of eight data
pin groups, one per each configuration. Most of the groups
share the same pin/mux array. Only the 18-bit configuration
needs a separate pin/mux array since in combines interleaved
data pins.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This groups VIN0 HSYNC and VSYNC pins together
since one cannot be used without another.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

This drops superfluous "signal" word from the pin group names
and renames data_enable group to clkenb as in the h/w manual.
Signed-off-by: NValentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

SH_PFC_PIN_GROUP(), pins[], mux[], defines
 clk, sync, ss1, ss2, rx, tx
But, msiof?_groups[] defines
 clk, ctrl, data

Fix msiof[012]_groups members to be consistent to PIN_GROUP.
Signed-off-by: NTakashi Yoshii <takasi-y@ops.dti.ne.jp>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

The macro is defined identically in four different locations. Share it.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

We had a compilation failure on x86_64 due to missing OF support
as this was an implicit dependency. Add an explicit dependency
on OF and OF_IRQ on the SoC driver.

Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Total failure with older approaches: what we need to do is
  have the *SoC subdriver* depend on OF and OF_IRQ. This is
  because the placeholder bool PINCTRL_MSM cannot cascade its
  dependencies when a subdriver selects it, Kconfig is smart
  but not that smart.
ChangeLog v1->v2:
- OK so "depends on OF" did not work here let's try to simply
  select OF and OF_IRQ for this then? It's one of those
  "warning: (PINCTRL_MSM8X74) selects PINCTRL_MSM which has
  unmet direct dependencies (PINCTRL && OF)" that I simply
  cannot find my way out of :-/