The cpufreq-dt-platdev driver supports creation of cpufreq-dt platform
device now, reuse that and remove similar code from platform code.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

In preparation for performing additional configuration prior to bringing
up L2, move the slcr initialization earlier in the boot process.
Signed-off-by: NJosh Cartwright <joshc@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Seeing the 'of' characters in a symbol that is being called from
ACPI seems to freak out people. So let's do a bit of pointless
renaming so that these folks do feel at home.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: NHanjun Guo <hanjun.guo@linaro.org>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Tested-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Now that the GIC chip implementation enables IRQCHIP_SKIP_SET_WAKE and
IRQCHIP_MASK_ON_SUSPEND by default, the platforms requiring them need
not override the irqchip flags as before.

This patch removes all the users of gic_set_irqchip_flags and the
function itself.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1436971109-20189-2-git-send-email-sudeep.holla@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This patch is based on the
commit 1a8e41cd ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
(cache controller) AuxCtlr register")

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

For Zynq, this fix avoids memory inconsistencies between Gigabit
Ethernet controller (GEM) and CPU when DMA_CMA is disabled.
Suggested-by: NPunnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: NThomas Betker <thomas.betker@rohde-schwarz.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.

Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: NJosh Cartwright <joshc@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1426088737-15817-5-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Based on
"mfd: syscon: Decouple syscon interface from platform devices"
(sha1: bdb0066d)
SLCR driver can use syscon/regmap drivers directly.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The naming convention of this driver was always under the scanner, people
complained that it should have a more generic name than cpu0, as it manages all
CPUs that are sharing clock lines.

Also, in future it will be modified to support any number of clusters with
separate clock/voltage lines.

Lets rename it to 'cpufreq_dt' from 'cpufreq_cpu0'.
Tested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

AUX setting has no effect that's why remove it.

Warning log:
L2C: platform provided aux values match the hardware, so
have no effect.  Please remove them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Provide information through SOC_BUS to user space.
Silicon revision is provided through devcfg device.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Move of_clk_init() from clock driver to enable
options not to use zynq clock driver.
Use for example fixed clock setting.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The generic cpufreq-cpu0 driver can scale the CPU frequency on Zynq
SOCs. Add the required platform device to the BSP and appropriate
OPPs to the dts.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

Reserve space from 0x0 - __pa(swapper_pg_dir),
if kernel is loaded from 0, which is not DMAable.
It is causing problem with MMC driver and others
which want to add dma buffers to this space.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Split the slcr into an early part for unlocking and cpu starting
and a later syscon driver.
Also add "syscon" compatible property for slcr.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Preparation step for next changes.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq is able to wake up on any IRQ, so flag it with
IRQCHIP_SKIP_SET_WAKE, and we want to mask off the IRQs when
going to suspend to avoid transient effects so also flag
this with IRQCHIP_MASK_ON_SUSPEND.

This is essentially, making the same changes as commit
'ARM: ux500: set proper GIC flags'
(sha1: 7e1f97ea) for Zynq.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

All new boards should be using this function instead of
of_platform_bus_probe.

Two side effects:
1. Possible to probe node which are not in the bus
2. Remove bus_id table from platform code
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

As the ux500 and the kirkwood driver, make the zynq driver a platform driver
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>

Fix the following compilation warning:

  arch/arm/mach-zynq/common.c:110:2: warning: initialization from incompatible pointer type [enabled by default]
  arch/arm/mach-zynq/common.c:110:2: warning: (near initialization for ‘__mach_desc_XILINX_EP107.restart’) [enabled by default]
Signed-off-by: NVincent Stehlé <vincent.stehle@freescale.com>
Cc: Robin Holt <holt@sgi.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: trivial@kernel.org
Signed-off-by: NOlof Johansson <olof@lixom.net>

The zynq platform code only supports DT based booting, so we
should use DT_MACHINE_START rather than MACHINE_START.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Michal Simek <michal.simek@xilinx.com>

It is not necessary to have board specific compatibility strings
in the platform code. The board dts files can use the more generic
'xlnx,zynq-7000' string.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is
specified") removed the need to explictly setup the init_irq field in
the machine description when using only irqchip_init. Remove that
declaration for zynq as well.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zynq is dual core Cortex A9 which starts always
at zero. Using simple trampoline ensure long jump
to secondary_startup code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>

Xilinx is vendor name not SoC name. Use zynq instead.

Also remove one checkpatch warning:
WARNING: static const char * array should probably be
static const char * const
+static const char *xilinx_dt_match[] = {
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Do system reset via slcr registers.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Create separate slcr driver instead of polluting common code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use Cortex a9 cp15 to read scu baseaddress.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use clocksource timer initialization.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.

Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The patch: "ARM: use common irqchip_init for GIC init"
(sha1: 0529e315)
should also add linux/irqchip.h header.

Error message:
arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init'
  undeclared here (not in a function)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The acronym PSS is deprecated by Xilinx. The correct term, which is
also used in Xilinx documentation is PS (processing system).
This is just a search and replace:
 - s/PSS/PS/g
 - s/pss/ps/g
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Tested-by: NJosh Cartwright <josh.cartwright@ni.com>

The patch: "ARM: use common irqchip_init for GIC init"
(sha1: 0529e315)
should also add linux/irqchip.h header.

Error message:
arch/arm/mach-zynq/common.c:99:14: error: 'irqchip_init'
  undeclared here (not in a function)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Convert all GIC DT initialization over to use common irqchip_init
function.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>

Now that the GIC initialization sets up the handle_arch_irq pointer, we
can remove it for all machines and make it static.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Anton Vorontsov <avorontsov@mvista.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>