SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.

This patch updates existing SPEAr machine support to adapt for common clock
framework.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

With common clock framework, it is must to call clk_{un}prepare() before/after
clk_{dis}enable. This patch fixes this for SPEAr timer.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:

Fout= Fin/((2 ^ (N+1)) * (M+1))

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:

Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
     0-13 (fractional part)
     14-16 (integer part)
     div is (16-14 bits).(13-0 bits) (in binary)

     Fout = Fin/(2 * div)
     Fout = ((Fin / 10000)/(2 * div)) * 10000
     Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
     Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000

div << 14 is simply 17 bit value written at register.

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.

Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2		EQ1
Fout2 = Fin * X/Y		EQ2

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

* depends/rmk/clkdev:
  CLKDEV: provide helpers for common clock framework
  ARM: 7392/1: CLKDEV: Optimize clk_find()
  ARM: 7376/1: clkdev: Implement managed clk_get()

Mike Turquette <mturquette@ti.com> has asked me to take the clock
changes through the arm-soc tree while there are still so many
inderdependencies, so this is the entire branch.

* depends/clk/clk-next: (30 commits)
  clk: add a fixed factor clock
  clk: mux: assign init data
  clk: remove COMMON_CLK_DISABLE_UNUSED
  clk: prevent spurious parent rate propagation
  MAINTAINERS: add entry for common clk framework
  clk: clk_set_rate() must fail if CLK_SET_RATE_GATE is set and clk is enabled
  clk: Use a separate struct for holding init data.
  clk: constify parent name arrays in macros
  clk: remove trailing whitespace from clk.h
  clk: select CLKDEV_LOOKUP for COMMON_CLK
  clk: Don't set clk->new_rate twice
  clk: clk-private: Add DEFINE_CLK macro
  clk: clk-gate: Create clk_gate_endisable()
  clk: Fix typo in comment
  clk: propagate round_rate for CLK_SET_RATE_PARENT case
  clk: pass parent_rate into .set_rate
  clk: always pass parent_rate into .round_rate
  clk: basic: improve parent_names & return errors
  clk: core: copy parent_names & return error codes
  clk: Constify parent name arrays
  ...
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Having fixed factors/dividers in hardware is a common pattern, so
add a basic clock type doing this. It basically describes a fixed
factor clock using a nominator and a denominator.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: NViresh Kumar <viresh.kumar@st.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
[mturquette@linaro.org: constify parent_names in static init macro]
[mturquette@linaro.org: copy/paste bug from mux in static init macro]
[mturquette@linaro.org: fix error handling in clk_register_fixed_factor]
[mturquette@linaro.org: improve division accuracy; thanks to Saravana]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The original conversion to struct clk_hw_init failed to add the pointer
assignment in clk_register_mux.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Reported-by: NSascha Hauer <s.hauer@pengutronix.de>

Exposing this option generates confusion and incorrect behavior for
single-image builds across platforms.  Enable this behavior permanently.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NSaravana Kannan <skannan@codeaurora.org>

Patch 'clk: always pass parent_rate into .round_rate' made a subtle
change to the semantics of .round_rate.  It is now expected for the
parent's rate to always be passed in, simplifying the implemenation of
various .round_rate callback definitions.

However the patch also introduced a bug in clk_calc_new_rates whereby a
clock without the CLK_SET_RATE_PARENT flag set could still propagate a
rate change up to a parent clock if the the .round_rate callback
modified the &best_parent_rate value in any way.

This patch fixes the issue at the framework level (in
clk_calc_new_rates) by specifically handling the case where the
CLK_SET_RATE_PARENT flag is not set.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NMike Turquette <mturquette@linaro.org>

The common clock framework allocates clocks dynamically.  Provide a
set of helpers to streamline the clkdev registration of the clock
lookups to avoid repetitive code sequences.
Reviewed-by: NViresh Kumar <viresh.kumar@st.com>
Tested-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This is well documented but isn't implemented. clk_set_rate() must check if
flags have CLK_SET_RATE_GATE bit set and is enabled too.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Create a struct clk_init_data to hold all data that needs to be passed from
the platfrom specific driver to the common clock framework during clock
registration. Add a pointer to this struct inside clk_hw.

This has several advantages:
* Completely hides struct clk from many clock platform drivers and static
  clock initialization code that don't care for static initialization of
  the struct clks.
* For platforms that want to do complete static initialization, it removed
  the need to directly mess with the struct clk's fields while still
  allowing to statically allocate struct clk. This keeps the code more
  future proof even if they include clk-private.h.
* Simplifies the generic clk_register() function and allows adding optional
  fields in the future without modifying the function signature.
* Simplifies the static initialization of clocks on all platforms by
  removing the need for forward delcarations or convoluted macros.
Signed-off-by: NSaravana Kannan <skannan@codeaurora.org>
[mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>

parent name array is now expected to be const char *, make
the relevent changes in the clk macros which define
default clock types.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Remove trailing whitespace from 2 lines.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Using the common clock infrastructure without the common clkdev code makes
little sense, so select CLKDEV_LOOKUP for COMMON_CLK.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) is true, then
we don't need to set clk->new_rate here, as we will call clk_calc_subtree()
afterwards and it also sets clk->new_rate.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

All macros used for creating different kind of clocks have similar code for
initializing struct clk. This patch removes those redundant lines and create
another macro DEFINE_CLK.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch tries to remove duplicate code for clk_gate clocks. This creates
another routine clk_gate_endisable() which will take care of enable/disable
clock with knowledge of CLK_GATE_SET_TO_DISABLE flag.

It works on following logic:

For enabling clock, enable = 1
	set2dis = 1	-> clear bit	-> set = 0
	set2dis = 0	-> set bit	-> set = 1

For disabling clock, enable = 0
	set2dis = 1	-> set bit	-> set = 1
	set2dis = 0	-> clear bit	-> set = 0

So, result is always: enable xor set2dis.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

CLK_MUX_INDEX_BIT is mistakenly written as CLK_MUX_INDEX_BITWISE in comment. Fix
it.

CLK_GATE_SET_TO_DISABLE is mistakenly written as CLK_GATE_SET_DISABLE in
comment. Fix it.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Need to propagate round_rate call for the clk that has no .round_rate
operation but with flag CLK_SET_RATE_PARENT set.

For example, clk_mux is a clk with no .round_rate operation.  However,
it could likely be in a clk_set_rate propagation path, saying it has
parent clk who has .round_rate and .set_rate operations.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

For most of .set_rate implementation, parent_rate will be used, so just
like passing parent_rate into .recalc_rate, let's pass parent_rate into
.set_rate too.

It also updates the kernel doc for .set_rate ops.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The parent_rate will likely be used by most .round_rate implementation
no matter whether flag CLK_SET_RATE_PARENT is set or not, so let's
always pass parent_rate into .round_rate.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch is the basic clk version of 'clk: core: copy parent_names &
return error codes'.

The registration functions are changed to allow the core code to copy
the array of strings and allow platforms to declare those arrays as
__initdata.

This patch also converts all of the basic clk registration functions to
return error codes which better aligns them with the existing clk.h api.
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch cleans up clk_register and solves a few bugs by teaching
clk_register and __clk_init to return error codes (instead of just NULL)
to better align with the existing clk.h api.

Along with that change this patch also introduces a new behavior whereby
clk_register copies the parent_names array, thus allowing platforms to
declare their parent_names arrays as __initdata.
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Drivers should be able to declare their arrays of parent names as const
so the APIs need to accept const arguments.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
[mturquette@linaro.org: constified gate]
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The comment is inaccurate (it actually ends the CONFIG_COMMON_CLK
section, there's no else) and given that we've just got a single level
of ifdef isn't really needed anyway.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Most users of clk_get_rate() actually assume a non zero
return value as a valid rate returned. Returing -EINVAL
might confuse such users, so make it instead return zero
on error.

Besides the return value of clk_get_rate seems to be
'unsigned long'.
Signed-off-by: NRajendra nayak <rnayak@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Besides the static initialization, the clk_ops of basic clks could
also be used by particular clk type being subclass of the basic clks.

For example, clk_busy_divider has the same clk_ops as clk_divider,
except it has to wait for a busy bit before return success with
.set_rate.  clk_busy_divider will somehow reuse clk_ops of clk_divider.

Since clk-provider.h is included by clk-private.h, it's safe to move
those clk_ops declaration of basic clks form  clk-private.h into
clk-provider.h, so that implementation of clks like clk_busy_divider
above do not need to include clk-private.h to access those clk_ops.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The clk_ops of basic clks should have "const" to match the definition
in "struct clk" and clk_register prototype.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

It makes no sense to have EXPORT_SYMBOL_GPL on static functions.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Change clk_register_mux to use kzalloc, just like what all other basic
clk registration functions do.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Documentation/clk.txt has some handsome ASCII art outlining which
clk_ops are mandatory for a given clock, given the capability of the
hardware.  Enforce those mandates with sanity checks in __clk_init.
Signed-off-by: NMike Turquette <mturquette@linaro.org>

It is possible to call clk_set_rate on a clock with a NULL parent.  One
such example is an adjustable-rate root clock.  Ensure that
clk_calc_new_rates does not dereference parent without checking first
and also handle the corner cases gracefully.
Reported-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Some static inline dummy functions were left over from before the clock
core was consolidated from several C files down to one.  Remove them.
Reported-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Remove old and misleading documentation from the previous clk_set_rate
implementaion.
Reported-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>