1. 27 1月, 2015 1 次提交
  2. 13 1月, 2015 1 次提交
  3. 01 11月, 2014 1 次提交
  4. 19 6月, 2014 1 次提交
  5. 11 6月, 2014 1 次提交
    • V
      drm/i915: Avoid div-by-zero when pixel_multiplier is zero · 2b85886a
      Ville Syrjälä 提交于
      On certain platforms pixel_multiplier is read out in
      .get_pipe_config(), but it also gets used to calculate the
      pixel clock in intel_sdvo_get_config(). If the pipe is disable
      but some SDVO outputs are active, we may end up dividing by zero
      in intel_sdvo_get_config().
      
      To avoid the problem simply check for zero pixel_multiplier and skip
      the division. Another attempt at fixing this involved populating
      pixel_multiplier to 1 even for disabled pipes, but that triggered a
      WARN because SDVO_CMD_GET_CLOCK_RATE_MULT command failed and thus
      encoder_pixel_multiplier was left at zero and didn't match
      pipe_config->pixel_multiplier.
      
      The "divide by pixel_multiplier" operation got introduced here:
       commit 18442d08
       Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
       Date:   Fri Sep 13 16:00:08 2013 +0300
      
          drm/i915: Fix port_clock and adjusted_mode.clock readout all over
      
      and it has caused a regression on certain machines since they would
      hit the div-by-zero during resume.
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76520
      Cc: <stable@vger.kernel.org> # 3.13+
      Tested-by: NTim Richardson <tim@tim-richardson.net>
      Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      2b85886a
  6. 04 6月, 2014 1 次提交
  7. 16 5月, 2014 3 次提交
  8. 07 5月, 2014 1 次提交
  9. 05 5月, 2014 1 次提交
    • D
      drm/i915/sdvo: Remove ->mode_set callback · 192d47a6
      Daniel Vetter 提交于
      SDVO is used by both crtcs using the i9xx_ and the ironlake_
      functions. For both cases there is nothing between the
      encoder->mode_set and the encoder->pre_enable calls that touches the
      hardware.
      
      The vlv_ functions are different since they enable the pll before the
      ->pre_enable hook. But SDVO isn't supported on vlv platforms, so this
      doesn't matter.
      
      We've also already clean up all the sdvo state computation logic, all
      relevant parts are already in the ->compute_config hook.  So we can
      just get rid of the ->mode_set hook by converting it to a ->pre_enable
      hook.
      Reviewed-by: NImre Deak <imre.deak@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      192d47a6
  10. 16 4月, 2014 1 次提交
  11. 21 3月, 2014 1 次提交
  12. 11 3月, 2014 1 次提交
    • V
      drm/i915: Make encoder cloning more flexible · bc079e8b
      Ville Syrjälä 提交于
      Currently we allow encoders to indicate whether they can be part of a
      cloned set with just one flag. That's not flexible enough to describe
      the actual hardware capabilities. Instead make it a bitmask of encoder
      types with which the current encoder can be cloned.
      
      For now we set the bitmask to allow DVO+DVO and DVO+VGA, which should
      match what the old boolean flag allowed. We will add some more cloning
      options in the future.
      
      Note that this patch also removes the encoder.possible_clones setting
      from encoder setup code - we compute this dynamically.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NRodrigo Vivi <rodrigo.vivi@gmail.com>
      [danvet: Add Ville's explanation why removing the encoder
      possible_clones is save.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      bc079e8b
  13. 14 2月, 2014 3 次提交
  14. 10 12月, 2013 1 次提交
  15. 28 11月, 2013 2 次提交
  16. 01 10月, 2013 4 次提交
  17. 17 9月, 2013 1 次提交
    • V
      drm/i915: Fix port_clock and adjusted_mode.clock readout all over · 18442d08
      Ville Syrjälä 提交于
      Now that adjusted_mode.clock no longer contains the pixel_multiplier, we
      can kill the get_clock() callback and instead do the clock readout
      in get_pipe_config().
      
      Also i9xx_crtc_clock_get() can now extract the frequency of the PCH
      DPLL, so use it to populate port_clock accurately for PCH encoders.
      For DP in port A the encoder is still responsible for filling in
      port_clock. The FDI adjusted_mode.clock extraction is kept in place
      for some extra sanity checking, but we no longer need to pretend it's
      also the port_clock.
      
      In the encoder get_config() functions fill out adjusted_mode.clock
      based on port_clock and other details such as the DP M/N values,
      HDMI 12bpc and SDVO pixel_multiplier. For PCH encoders we will then
      do an extra sanity check to make sure the dotclock we derived from
      the FDI configuratiuon matches the one we derive from port_clock.
      
      DVO doesn't exist on PCH platforms, so it doesn't need to anything
      but assign adjusted_mode.clock=port_clock. And DDI is HSW only, so
      none of the changes apply there.
      
      v2: Use hdmi_reg color format to detect 12bpc HDMI case
      v3: Set adjusted_mode.clock for LVDS too
      v4: Rename ironlake_crtc_clock_get to ironlake_pch_clock_get,
          eliminate the useless link_freq variable.
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      18442d08
  18. 13 9月, 2013 1 次提交
  19. 12 9月, 2013 1 次提交
    • D
      drm/i915/sdvo: Robustify the dtd<->drm_mode conversions · 1c4a814e
      Daniel Vetter 提交于
      We've failed to properly clear out the flags when converting a dtd to
      a drm mode. For more paranoia just memset the entire structure (and
      drop the now redundant clears).
      
      Also since
      
      commit 135c81b8
      Author: Daniel Vetter <daniel.vetter@ffwll.ch>
      Date:   Sun Jul 21 21:37:09 2013 +0200
      
          drm/i915: clean up crtc timings computation
      
      we don't update the crtc timings any more properly, so do that again.
      
      v2: Remove more redundant clearing, spotted by Ville.
      
      v3: Actually make it compile. Oops.
      
      v4: Use a temporary structure to fill in the mode and copy it over
      with drm_mode_copy. This will ensure we don't clobber the mode list or
      id. Suggested by Ville.
      
      Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reported-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      [danvet: Use the = {}; structure clearing instead of memset as
      suggested by Ville.]
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      1c4a814e
  20. 10 9月, 2013 1 次提交
  21. 06 9月, 2013 1 次提交
  22. 04 9月, 2013 1 次提交
  23. 22 8月, 2013 1 次提交
  24. 08 8月, 2013 1 次提交
  25. 05 8月, 2013 1 次提交
  26. 24 7月, 2013 1 次提交
  27. 12 7月, 2013 1 次提交
  28. 01 7月, 2013 1 次提交
  29. 12 6月, 2013 1 次提交
  30. 11 6月, 2013 2 次提交
  31. 10 6月, 2013 1 次提交
    • D
      drm/i915: prefer VBT modes for SVDO-LVDS over EDID · c3456fb3
      Daniel Vetter 提交于
      In
      
      commit 53d3b4d7
      Author: Egbert Eich <eich@suse.de>
      Date:   Tue Jun 4 17:13:21 2013 +0200
      
          drm/i915/sdvo: Use &intel_sdvo->ddc instead of intel_sdvo->i2c for DDC
      
      Egbert Eich fixed a long-standing bug where we simply used a
      non-working i2c controller to read the EDID for SDVO-LVDS panels.
      Unfortunately some machines seem to not be able to cope with the mode
      provided in the EDID. Specifically they seem to not be able to cope
      with a 4x pixel mutliplier instead of a 2x one, which seems to have
      been worked around by slightly changing the panels native mode in the
      VBT so that the dotclock is just barely above 50MHz.
      
      Since it took forever to notice the breakage it's fairly safe to
      assume that at least for SDVO-LVDS panels the VBT contains fairly sane
      data. So just switch around the order and use VBT modes first.
      
      v2: Also add EDID modes just in case, and spell Egbert correctly.
      
      v3: Elaborate a bit more about what's going on on Chris' machine.
      
      Cc: Egbert Eich <eich@suse.de>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65524
      Cc: stable@vger.kernel.org
      Reported-and-tested-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      c3456fb3