1. 27 6月, 2017 1 次提交
    • R
      powerpc/powernv/pci: Dynamically allocate PHB diag data · 5cb1f8fd
      Russell Currey 提交于
      Diagnostic data for PHBs currently works by allocated a fixed-sized buffer.
      This is simple, but either wastes memory (though only a few kilobytes) or
      in the case of PHB4 isn't enough to fit the whole data blob.
      
      For machines that don't describe the diagnostic data size in the device
      tree, use the hardcoded buffer size as before.  For those that do, only
      allocate exactly what's needed.
      
      In the special case of P7IOC (which has two types of diag data), the larger
      should be specified in the device tree.
      Signed-off-by: NRussell Currey <ruscur@russell.cc>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      5cb1f8fd
  2. 04 5月, 2017 1 次提交
  3. 03 5月, 2017 1 次提交
  4. 22 11月, 2016 1 次提交
    • R
      powerpc/pci: Always print PHB and PE numbers as hexadecimal · 1f52f176
      Russell Currey 提交于
      PHB, PE (and by association MVE) numbers are printed as a mix of decimal
      and hexadecimal throughout the kernel.  This can be misleading, so make
      them all hexadecimal.
      
      Standardising on hex instead of dec because:
      
       - PHB numbers are presented in hex in sysfs/debugfs (and lspci, etc)
       - PE numbers are presented as hex in sysfs and parsed in hex in debugfs
      
      The only place I think this could cause confusing are the messages during
      boot, i.e.
      
      	pci 000a:01     : [PE# 000] Secondary bus 1 associated with PE#0
      
      which can be a quick way to check PE numbers.  pe_level_printk() will
      only print two characters instead of three, so the above would be
      
      	pci 000a:01     : [PE# 00] Secondary bus 1 associated with PE#0
      
      which gives a hint it's in hex.
      Signed-off-by: NRussell Currey <ruscur@russell.cc>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      1f52f176
  5. 04 10月, 2016 2 次提交
  6. 29 9月, 2016 1 次提交
  7. 23 9月, 2016 2 次提交
  8. 21 6月, 2016 2 次提交
  9. 12 5月, 2016 1 次提交
    • M
      Revert "powerpc/powernv: Exclude root bus in pnv_pci_reset_secondary_bus()" · 848912e5
      Michael Ellerman 提交于
      This reverts commit c8ceacc2.
      
      Gavin says: I missed the fact that it affects the PCI passthrou path as
      reported by Alexey: When passing GPU (0003:01:00.0) which seats behind
      the root port, the reset request is routed to skiboot in original code.
      In skiboot, the link bouncing events are masked during the reset. So we
      don't see EEH (freeze all) error even link bouncing happens. With the
      changes included, the reset is done by kernel and the link bouncing
      events aren't masked by altering content of PHB3 (or P7IOC) specific
      hardware registers which are invisible to kernel (skiboot hides the
      hardware specific). It means the link bouncing is seen by the root port
      and it causes a EEH (freeze all) error. The PCI passthrough on GPU
      device cannot work.
      Requested-by: NAlexey Kardashevskiy <aik@ozlabs.ru>
      Requested-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      848912e5
  10. 11 5月, 2016 3 次提交
  11. 09 3月, 2016 3 次提交
    • W
      powerpc/powernv: Support PCI config restore for VFs · 0dc2830e
      Wei Yang 提交于
      After PE reset, OPAL API opal_pci_reinit() is called on all devices
      contained in the PE to reinitialize them. While skiboot is not aware of
      VFs, we have to implement the function in kernel to reinitialize VFs after
      reset on PE for VFs.
      
      In this patch, two functions pnv_pci_fixup_vf_mps() and
      pnv_eeh_restore_vf_config() both manipulate the MPS of the VF, since for a
      VF it has three cases.
      
      1. Normal creation for a VF
         In this case, pnv_pci_fixup_vf_mps() is called to make the MPS a proper
         value compared with its parent.
      2. EEH recovery without VF removed
         In this case, MPS is stored in pci_dn and pnv_eeh_restore_vf_config() is
         called to restore it and reinitialize other part.
      3. EEH recovery with VF removed
         In this case, VF will be removed then re-created. Both functions are
         called. First pnv_pci_fixup_vf_mps() is called to store the proper MPS
         to pci_dn and then pnv_eeh_restore_vf_config() is called to do proper
         thing.
      
      This introduces two functions: pnv_pci_fixup_vf_mps() to fixup the VF's
      MPS to make sure it is equal to parent's and store this value in pci_dn
      for future use. pnv_eeh_restore_vf_config() to re-initialize on VF by
      restoring MPS, disabling completion timeout, enabling SERR, etc.
      Signed-off-by: NWei Yang <weiyang@linux.vnet.ibm.com>
      Acked-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      0dc2830e
    • W
      powerpc/powernv: Support EEH reset for VF PE · 9312bc5b
      Wei Yang 提交于
      PEs for VFs don't have primary bus. So they have to have their own reset
      backend, which is used during EEH recovery. The patch implements the reset
      backend for VF's PE by issuing FLR or AF FLR to the VFs, which are contained
      in the PE.
      Signed-off-by: NWei Yang <weiyang@linux.vnet.ibm.com>
      Acked-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      9312bc5b
    • W
      powerpc/eeh: Create PE for VFs · c29fa27d
      Wei Yang 提交于
      This creates PEs for VFs in the weak function pcibios_bus_add_device().
      Those PEs for VFs are identified with newly introduced flag EEH_PE_VF
      so that we treat them differently during EEH recovery.
      Signed-off-by: NWei Yang <weiyang@linux.vnet.ibm.com>
      Acked-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      c29fa27d
  12. 15 2月, 2016 1 次提交
  13. 10 2月, 2016 1 次提交
  14. 17 12月, 2015 1 次提交
  15. 21 10月, 2015 4 次提交
  16. 30 7月, 2015 1 次提交
  17. 21 7月, 2015 2 次提交
  18. 22 5月, 2015 1 次提交
  19. 13 5月, 2015 2 次提交
  20. 24 3月, 2015 3 次提交
  21. 17 3月, 2015 6 次提交