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  1. 24 1月, 2016 2 次提交
  3. 23 10月, 2015 1 次提交
    • J
      spi/bcm63xx: move register definitions into the driver · 44d8fb30
      由 Jonas Gorski 提交于 
      Move all register definitions and structs into the driver. This allows
us dropping the platform_data struct and drop any arch specific
includes. Make use of different device names to identify the version of
the block we have.

Since we now have full control over the message width, we can drop the
size check, which was broken anyway, since it never set ret to any error
code.

Also since we now have no arch depedendent resources, we can now allow
compiling it for any arch, hidden behind COMPILE_TEST.
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      44d8fb30
  5. 13 10月, 2015 1 次提交
  7. 03 9月, 2015 1 次提交
    • A
      MIPS: Remove all the uses of custom gpio.h · 832f5dac
      由 Alban Bedel 提交于 
      Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS
machines, and each machine type provides its own gpio.h. However
only a handful really implement the GPIO API, most just forward
everythings to gpiolib.

The Alchemy machine is notable as it provides a system to allow
implementing the GPIO API at the board level. But it is not used by
any board currently supported, so it can also be removed.

For most machine types we can just remove the custom gpio.h, as well
as the custom wrappers if some exists. Some of the code found in
the wrappers must be moved to the respective GPIO driver.

A few more fixes are need in some drivers as they rely on linux/gpio.h
to provides some machine specific definitions, or used asm/gpio.h
instead of linux/gpio.h for the gpio API.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: linux-mips@linux-mips.org
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Daniel Walter <dwalter@google.com>
Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Varka Bhadram <varkabhadram@gmail.com>
Cc: Masanari Iida <standby24x7@gmail.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Michael Buesch <m@bues.ch>
Cc: abdoulaye berthe <berthe.ab@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-ide@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-input@vger.kernel.org
Cc: netdev@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10828/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      832f5dac
  9. 03 8月, 2015 1 次提交
  11. 22 6月, 2015 1 次提交
  13. 09 4月, 2015 1 次提交
  15. 31 3月, 2015 1 次提交
  17. 01 3月, 2015 1 次提交
  19. 25 11月, 2014 1 次提交
  21. 30 7月, 2014 6 次提交
  23. 23 1月, 2014 4 次提交
  25. 06 8月, 2013 1 次提交
  27. 01 7月, 2013 3 次提交
  29. 14 6月, 2013 1 次提交
    • F
      bcm63xx_enet: add support Broadcom BCM6345 Ethernet · 3dc6475c
      由 Florian Fainelli 提交于 
      This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
has a slightly different and older DMA engine which requires the
following modifications:

- the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
  which means that the helpers enet_dma{c,s} need to account for this
  channel width and we can no longer use macros

- BCM6345 DMA engine does not have any internal SRAM for transfering
  buffers

- BCM6345 buffer allocation and flow control is not per-channel but
  global (done in RSET_ENETDMA)

- the DMA engine bits are right-shifted by 3 compared to other DMA
  generations

- the DMA enable/interrupt masks are a little different (we need to
  enabled more bits for 6345)

- some register have the same meaning but are offsetted in the ENET_DMAC
  space so a lookup table is required to return the proper offset

The MAC itself is identical and requires no modifications to work.
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3dc6475c
  31. 11 6月, 2013 2 次提交
    • M
      bcm63xx_enet: add support for Broadcom BCM63xx integrated gigabit switch · 6f00a022
      由 Maxime Bizon 提交于 
      Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch
which needs to be driven slightly differently from the traditional
external switches. This patch introduces changes in arch/mips/bcm63xx in order
to:

- register a bcm63xx_enetsw driver instead of bcm63xx_enet driver
- update DMA channels configuration & state RAM base addresses
- add a new platform data configuration knob to define the number of
  ports per switch/device and force link on some ports
- define the required switch registers

On the driver side, the following changes are required:

- the switch ports need to be polled to ensure the link is up and
  running and RX/TX can properly work
- basic switch configuration needs to be performed for the switch to
  forward packets to the CPU
- update the MIB counters since the integrated
Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6f00a022
    • M
      bcm63xx_enet: split DMA channel register accesses · 0ae99b5f
      由 Maxime Bizon 提交于 
      The current bcm63xx_enet driver always uses bcmenet_shared_base whenever
it needs to access DMA channel configuration space or access the DMA
channel state RAM. Split these register in 3 parts to be more accurate:

- global DMA configuration
- per DMA channel configuration space
- per DMA channel state RAM space

This is preliminary to support new chips where the global DMA
configuration remains the same, but there is a varying number of DMA
channels located at a different memory offset.
Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
Signed-off-by: NJonas Gorski <jogo@openwrt.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0ae99b5f
  33. 08 5月, 2013 7 次提交
  35. 08 4月, 2013 1 次提交
  37. 20 3月, 2013 1 次提交
  39. 01 2月, 2013 1 次提交
  41. 14 12月, 2012 1 次提交
  43. 20 11月, 2012 1 次提交