1. 17 4月, 2008 7 次提交
    • G
      x86: move ipi definitions to mach_ipi.h · 5af5573e
      Glauber Costa 提交于
      take them out of the x86_64-only asm/mach_apic.h
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      5af5573e
    • R
      x86: apic_is_clustered_box to indicate unsynched TSC's on multiboard vSMP systems · 1cb68487
      Ravikiran G Thirumalai 提交于
      Indicate TSCs are unreliable as time sources if the platform is
      a multi chassi ScaleMP vSMPowered machine.
      Signed-off-by: NRavikiran Thirumalai <kiran@scalex86.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1cb68487
    • G
      x86: change boot_cpu_id to boot_cpu_physical_apicid · c70dcb74
      Glauber de Oliveira Costa 提交于
      This is to match i386. The former name was cuter,
      but the current is more meaningful and more general,
      since cpu_id can be a logical id.
      Signed-off-by: NGlauber Costa <gcosta@redhat.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c70dcb74
    • Y
      x86: get boot_cpu_id as early for k8_scan_nodes · 8643f9d0
      Yinghai Lu 提交于
      When acpi=off or there is no SRAT defined, apicid_to_node is got from K8
      Northbridge PCI configuration space in k8_scan_nodes() in
      arch/x86_64/mm/k8toplogy.c.
      
      The problem is that it assumes bsp apic id is 0 at that point.
      
      For four socket system with Quad core cpus installed, all cpus apic id
      is offset by 4, and bsp apic id is 4.
      
      For eight socket system with dual core cpus installed, all cpus apic id
      is offset by 2, and bsp apic id is 2.
      
      We need get boot_cpu_id --- bsp apic id, before k8_scan_nodes by called.
      
      So create early_acpi_boot_init and early_get_smp_config for get boot_cpu_id.
      Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8643f9d0
    • Y
      x86: apic_is_clustered_box for vsmp · f8fffa45
      Yinghai Lu 提交于
      quad core 8 socket system will have apic id lifting.the apic id range could
      be [4, 0x23]. and apic_is_clustered_box will think that need to three clusters
      and that is larger than 2. So it is treated as a clustered_box.
      
      and will get:
      
         Marking TSC unstable due to TSCs unsynchronized
      
      even if the CPUs have X86_FEATURE_CONSTANT_TSC set.
      
      this quick fix will check if the cpu is from AMD.
      
      but vsmp still needs that checking...
      
      this patch is fix to make sure that vsmp not to be passed.
      Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f8fffa45
    • Y
      x86: insert_resorce for lapic addr after e820_reserve_resources · 1e934dda
      Yinghai Lu 提交于
      when comparing the e820 direct from BIOS, and the one by kexec:
      
       BIOS-provided physical RAM map:
      - BIOS-e820: 0000000000000000 - 0000000000097400 (usable)
      + BIOS-e820: 0000000000000100 - 0000000000097400 (usable)
        BIOS-e820: 0000000000097400 - 00000000000a0000 (reserved)
        BIOS-e820: 00000000000e6000 - 0000000000100000 (reserved)
        BIOS-e820: 0000000000100000 - 00000000dffa0000 (usable)
      - BIOS-e820: 00000000dffae000 - 00000000dffb0000 type 9
      + BIOS-e820: 00000000dffae000 - 00000000dffb0000 (reserved)
        BIOS-e820: 00000000dffb0000 - 00000000dffbe000 (ACPI data)
        BIOS-e820: 00000000dffbe000 - 00000000dfff0000 (ACPI NVS)
        BIOS-e820: 00000000dfff0000 - 00000000e0000000 (reserved)
        BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved)
      - BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
                   =======> that is the local apic address... somewhere we lost it
        BIOS-e820: 00000000ff700000 - 0000000100000000 (reserved)
        BIOS-e820: 0000000100000000 - 0000004020000000 (usable)
      
      found one entry about reserved is missing for the kernel by kexec.
      
      it turns out init_apic_mappings is called before e820_reserve_resources
      in setup_arch. but e820_reserve_resources is using request_resource.
      it will not handle the conflicts.
      
      there are three ways to fix it:
      
      1. change request_resource in e820_reserve_resources to to insert_resource
      2. move init_apic_mappings after e820_reserve_resources
      3. use late_initcall to insert lapic resource.
      
      this patch is using method 3, that is less intrusive.
      
      in later version could consider to use method 1.
      
      before patch
      fed20000-ffffffff : PCI Bus #00
        fee00000-fee00fff : Local APIC
        fefff000-feffffff : pnp 00:09
        ff700000-ffffffff : reserved
      
      with patch will get map in first kernel
      
      fed20000-ffffffff : PCI Bus #00
        fee00000-fee00fff : Local APIC
          fee00000-fee00fff : reserved
        fefff000-feffffff : pnp 00:09
        ff700000-ffffffff : reserved
      Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      1e934dda
    • Y
      x86: make amd quad core 8 socket system not be clustered_box, #2 · 322850af
      Yinghai Lu 提交于
      quad core 8 socket system will have apic id lifting.the apic id range could
      be [4, 0x23]. and apic_is_clustered_box will think that need to three clusters
      and that is large than 2. So it is treated as clustered_box.
      
      and will get
      
      Marking TSC unstable due to TSCs unsynchronized
      
      even the CPUs have X86_FEATURE_CONSTANT_TSC set.
      
      this patch will check if the cpu is from AMD.
      Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      322850af
  2. 30 1月, 2008 19 次提交
  3. 25 1月, 2008 1 次提交
  4. 24 10月, 2007 1 次提交
  5. 18 10月, 2007 2 次提交
    • J
      x86: expand /proc/interrupts to include missing vectors, v2 · 38e760a1
      Joe Korty 提交于
      Add missing IRQs and IRQ descriptions to /proc/interrupts.
      
      /proc/interrupts is most useful when it displays every IRQ vector in use by
      the system, not just those somebody thought would be interesting.
      
      This patch inserts the following vector displays to the i386 and x86_64
      platforms, as appropriate:
      
      	rescheduling interrupts
      	TLB flush interrupts
      	function call interrupts
      	thermal event interrupts
      	threshold interrupts
      	spurious interrupts
      
      A threshold interrupt occurs when ECC memory correction is occuring at too
      high a frequency.  Thresholds are used by the ECC hardware as occasional
      ECC failures are part of normal operation, but long sequences of ECC
      failures usually indicate a memory chip that is about to fail.
      
      Thermal event interrupts occur when a temperature threshold has been
      exceeded for some CPU chip.  IIRC, a thermal interrupt is also generated
      when the temperature drops back to a normal level.
      
      A spurious interrupt is an interrupt that was raised then lowered by the
      device before it could be fully processed by the APIC.  Hence the apic sees
      the interrupt but does not know what device it came from.  For this case
      the APIC hardware will assume a vector of 0xff.
      
      Rescheduling, call, and TLB flush interrupts are sent from one CPU to
      another per the needs of the OS.  Typically, their statistics would be used
      to discover if an interrupt flood of the given type has been occuring.
      
      AK: merged v2 and v4 which had some more tweaks
      AK: replace Local interrupts with Local timer interrupts
      AK: Fixed description of interrupt types.
      
      [ tglx: arch/x86 adaptation ]
      [ mingo: small cleanup ]
      Signed-off-by: NJoe Korty <joe.korty@ccur.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Cc: Tim Hockin <thockin@hockin.org>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: "H. Peter Anvin" <hpa@zytor.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      38e760a1
    • T
      x86: C1E late detection fix. Really switch off lapic timer · 3dfbc884
      Thomas Gleixner 提交于
      Doh, I completely missed that devices marked DUMMY are not running
      the set_mode function. So we force broadcasting, but we keep the
      local APIC timer running.
      
      Let the clock event layer mark the device _after_ switching it off.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      3dfbc884
  6. 15 10月, 2007 1 次提交
    • T
      x86: force timer broadcast on late AMD C1E detection · 89039b37
      Thomas Gleixner 提交于
      The 64bit SMP bootup is slightly different to the 32bit one. It enables
      the boot CPU local APIC timer before all CPUs are brought up. Some AMD C1E
      systems have the C1E feature flag only set in the secondary CPU. Due to
      the early enable of the boot CPU local APIC timer the APIC timer is
      registered as a fully functional device. When we detect the wreckage during
      the bringup of the secondary CPU, we need to force the boot CPU into
      broadcast mode. 
      
      Check the C1E caused APIC timer disable, when the secondary APIC timer is
      initialized. If the boot CPU APIC timer was registered as a functional
      clock event device, then fix this up and utilize the
      CLOCK_EVT_NOTIFY_BROADCAST_FORCE mechanism to force the already
      registered boot CPU APIC timer into broadcast mode.
      
      Tested by force injecting the failure mode.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      89039b37
  7. 13 10月, 2007 9 次提交