- 28 5月, 2016 17 次提交
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由 James Hogan 提交于
Simplify the DSP instruction wrapper macros which use explicit encodings for microMIPS and normal MIPS by using the new encoding macros and removing duplication. To me this makes it easier to read since it is much shorter, but it also ensures .insn is used, preventing objdump disassembling the microMIPS code as normal MIPS. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13314/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Hardcoded MIPS instruction encodings are provided for tlbinvf, mfhc0 & mthc0 instructions, but microMIPS encodings are missing. I doubt any microMIPS cores exist at present which support these instructions, but the microMIPS encodings exist, and microMIPS cores may support them in the future. Add the missing microMIPS encodings using the new macros. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13313/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
When the toolchain doesn't support MSA we encode MSA instructions explicitly in assembly. Unfortunately we use .word for both MIPS and microMIPS encodings which is wrong, since 32-bit microMIPS instructions are made up from a pair of halfwords. - The most significant halfword always comes first, so for little endian builds the halves will be emitted in the wrong order. - 32-bit alignment isn't guaranteed, so the assembler may insert a 16-bit nop instruction to pad the instruction stream to a 32-bit boundary. Use the new instruction encoding macros to encode microMIPS MSA instructions correctly. Fixes: d96cc3d1 ("MIPS: Add microMIPS MSA support.") Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13312/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Toolchains may be used which support microMIPS but not VZ instructions (i.e. binutis 2.22 & 2.23), so extend the explicitly encoded versions of the guest COP0 register & guest TLB access macros to support microMIPS encodings too, using the new macros. This prevents non-microMIPS instructions being executed in microMIPS mode during CPU probe on cores supporting VZ (e.g. M5150), which cause reserved instruction exceptions early during boot. Fixes: bad50d79 ("MIPS: Fix VZ probe gas errors with binutils <2.24") Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13311/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
To allow simplification of macros which use inline assembly to explicitly encode instructions, add a few simple abstractions to mipsregs.h which expand to specific microMIPS or normal MIPS encodings depending on what type of kernel is being built: _ASM_INSN_IF_MIPS(_enc) : Emit a 32bit MIPS instruction if microMIPS is not enabled. _ASM_INSN32_IF_MM(_enc) : Emit a 32bit microMIPS instruction if enabled. _ASM_INSN16_IF_MM(_enc) : Emit a 16bit microMIPS instruction if enabled. The macros can be used one after another since the MIPS / microMIPS macros are mutually exclusive, for example: __asm__ __volatile__( ".set push\n\t" ".set noat\n\t" "# mfgc0 $1, $%1, %2\n\t" _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) "move %0, $1\n\t" ".set pop" : "=r" (__res) : "i" (source), "i" (sel)); Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13310/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
As noticed by Sergei in the discussion of Andrea Gelmini's patch series. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Reported-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: adam.buchbinder@gmail.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13328/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: david.daney@cavium.com Cc: janne.huttunen@nokia.com Cc: aaro.koskinen@nokia.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13324/ Patchwork: https://patchwork.linux-mips.org/patch/13325/ Patchwork: https://patchwork.linux-mips.org/patch/13326/ Patchwork: https://patchwork.linux-mips.org/patch/13327/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13323/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: chenhc@lemote.com Cc: viresh.kumar@linaro.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13322/ Patchwork: https://patchwork.linux-mips.org/patch/13332/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13321/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13320/ Patchwork: https://patchwork.linux-mips.org/patch/13335/ Patchwork: https://patchwork.linux-mips.org/patch/13336/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13319/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13318/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andrea Gelmini 提交于
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net> Cc: chenhc@lemote.com Cc: james.hogan@imgtec.com Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13317/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
The versions of the __write_{32,64}bit_gc0_register() macros for when there is no virt support in the assembler use the "J" inline asm constraint to allow integer zero, but this needs to be accompanied by the "z" formatting string so that it turns into $0. Fix both macros to do this. Fixes: bad50d79 ("MIPS: Fix VZ probe gas errors with binutils <2.24") Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13289/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Matt Redfearn 提交于
The SegCtl registers are standard for MIPSr3..MIPSr5. Add definitions of these registers and use them rather than constants Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Chris Packham <judge.packham@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13290/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 5月, 2016 2 次提交
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由 James Hogan 提交于
The VZ guest register & TLB access macros introduced in commit "MIPS: Add guest CP0 accessors" use VZ ASE specific instructions that aren't understood by versions of binutils prior to 2.24. Add a check for whether the toolchain supports the -mvirt option, similar to the MSA toolchain check, and implement the accessors using .word if not. Due to difficulty in converting compiler specified registers (e.g. "$3") to usable numbers (e.g. "3") in inline asm, we need to copy to/from a temporary register, namely the assembler temporary (at/$1), and specify guest CP0 registers numerically in the gc0 macros. Fixes: 7eb91118 ("MIPS: Add guest CP0 accessors") Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Reported-by: NGuenter Roeck <linux@roeck-us.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: linux-next@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13255/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Fix a build regression from commit c9017757 ("MIPS: init upper 64b of vector registers when MSA is first used"): arch/mips/built-in.o: In function `enable_restore_fp_context': traps.c:(.text+0xbb90): undefined reference to `_init_msa_upper' traps.c:(.text+0xbb90): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' traps.c:(.text+0xbef0): undefined reference to `_init_msa_upper' traps.c:(.text+0xbef0): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' to !CONFIG_CPU_HAS_MSA configurations with older GCC versions, which are unable to figure out that calls to `_init_msa_upper' are indeed dead. Of the many ways to tackle this failure choose the approach we have already taken in `thread_msa_context_live'. [ralf@linux-mips.org: Drop patch segment to junk file.] Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: stable@vger.kernel.org # v3.16+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13271/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 14 5月, 2016 2 次提交
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由 Tony Wu 提交于
Fix mips_cm_lock_other compilation error when MIPS_CM is not selected. This was introduced in commit 23d5de8e (MIPS: CM: Introduce core-other locking functions) Signed-off-by: NTony Wu <tung7970@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11698/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maarten ter Huurne 提交于
The DT fragment will select the ohci-platform driver, since that can handle the JZ4740 OHCI just fine. While I don't have a JZ4740-based board with anything connected to the USB host controller, I did test the generic OHCI driver successfully on a JZ4770-based board. The device is disabled by default; boards that want to use it can override the "status" property. The mass-production Qi LB60 boards don't use the USB host controller. Signed-off-by: NMaarten ter Huurne <maarten@treewalker.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Paul Cercueil <paul@crapouillou.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13104/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 13 5月, 2016 19 次提交
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由 Sashka Nochkin 提交于
Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used. However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM. The patch below reflects that. Signed-off-by: NSashka Nochkin <linux-mips@durdom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13135/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Remove a duplicate o32 `elf_check_arch' implementation, move all macro variants to <asm/elf.h> and define them unconditionally under indvidual names, substituting alias `elf_check_arch' definitions in variant code. Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13245/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13244/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Move the `mips_elf_abiflags_v0' structure and FP ABI flag macros outside #ifndef ELF_ARCH. These are public interfaces. Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13243/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Add a few new cpu-features.h definitions for VZ sub-features, namely the existence of the CP0_GuestCtl0Ext, CP0_GuestCtl1, and CP0_GuestCtl2 registers, and support for GuestID to dialias TLB entries belonging to different guests. Also add certain features present in the guest, with the naming scheme cpu_guest_has_*. These are added separately to the main options bitfield since they generally parallel similar features in the root context. A few of these (FPU, MSA, watchpoints, perf counters, CP0_[X]ContextConfig registers, MAAR registers, and probably others in future) can be dynamically configured in the guest context, for which the cpu_guest_has_dyn_* macros are added. [ralf@linux-mips.org: Resolve merge conflict.] Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13231/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Add guest CP0 accessors and guest TLB operations along the same lines as the existing macros and functions for the root CP0. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Acked-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13229/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Add various register definitions to <asm/mipsregs.h> for the coprocessor zero registers in the VZ ASE, namely CP0_GuestCtl0, CP0_GuestCtl0Ext, CP0_GuestCtl1, CP0_GuestCtl2, CP0_GuestCtl3, and CP0_GTOffset. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Acked-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13228/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
The decode_config4() function reads kscratch_mask from CP0_Config4.KScrExist using a hard coded shift and mask. We already have a definition for the mask in mipsregs.h, so add a definition for the shift and make use of them. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13227/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Add CPU feature for standard MIPS r2 performance counters, as determined by the Config1.PC bit. Both perf_events and oprofile probe this bit, so lets combine the probing and change both to use cpu_has_perf. This will also be used for VZ support in KVM to know whether performance counters exist which can be exposed to guests. [ralf@linux-mips.org: resolve conflict.] Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Robert Richter <rric@kernel.org> Cc: linux-mips@linux-mips.org Cc: oprofile-list@lists.sf.net Patchwork: https://patchwork.linux-mips.org/patch/13226/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
The CP0_[X]ContextConfig registers are present if CP0_Config3.CTXTC or CP0_Config3.SM are set, and provide more control over which bits of CP0_[X]Context are set to the faulting virtual address on a TLB exception. KVM/VZ will need to be able to save and restore these registers in the guest context, so add the relevant definitions and probing of the ContextConfig feature in the root context first. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13225/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
The optional CP0_BadInstr and CP0_BadInstrP registers are written with the encoding of the instruction that caused a synchronous exception to occur, and the prior branch instruction if in a delay slot. These will be useful for instruction emulation in KVM, and especially for VZ support where reading guest virtual memory is a bit more awkward. Add CPU option numbers and cpu_has_* definitions to indicate the presence of each registers, and add code to probe for them using bits in the CP0_Config3 register. [ralf@linux-mips.org: resolve merge conflict.] Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13224/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
The CP0_EBase register may optionally have a write gate (WG) bit to allow the upper bits to be written, i.e. bits 31:30 on MIPS32 since r3 (to allow for an exception base outside of KSeg0/KSeg1 when segmentation control is in use) and bits 63:30 on MIPS64 (which also implies the extension of CP0_EBase to 64 bits long). The presence of this feature will need to be known about for VZ support in order to correctly save and restore all the bits of the guest CP0_EBase register, so add CPU feature definition and probing for this feature. Probing the WG bit on MIPS64 can be a bit fiddly, since 64-bit COP0 register access instructions were UNDEFINED for 32-bit registers prior to MIPS r6, and it'd be nice to be able to probe without clobbering the existing state, so there are 3 potential paths: - If we do a 32-bit read of CP0_EBase and the WG bit is already set, the register must be 64-bit. - On MIPS r6 we can do a 64-bit read-modify-write to set CP0_EBase.WG, since the upper bits will read 0 and be ignored on write if the register is 32-bit. - On pre-r6 cores, we do a 32-bit read-modify-write of CP0_EBase. This avoids the potentially UNDEFINED behaviour, but will clobber the upper 32-bits of CP0_EBase if it isn't a simple sign extension (which also requires us to ensure BEV=1 or modifying the exception base would be UNDEFINED too). It is hopefully unlikely a bootloader would set up CP0_EBase to a 64-bit segment and leave WG=0. [ralf@linux-mips.org: Resolved merge conflict.] Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Tested-by: NMatt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13223/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 James Hogan 提交于
Add definitions for the bits & fields in the CP0_EBase register, and use them from a few different places in arch/mips which hardcoded these values. Signed-off-by: NJames Hogan <james.hogan@imgtec.com> Cc: Jayachandran C <jchandra@broadcom.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13222/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Florian Fainelli 提交于
Some processors, like Broadcom's BMIPS4380 and BMIPS5000 support RIXI and the "rotr" instruction, which can be used to get a slightly more efficient page table layout. Introduce a CONFIG_CPU_HAS_RIXI such that those cores can benefit from this feature. Perform the conditional check updates where relevant. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Cc: john@phrozen.org Cc: cernekee@gmail.com Cc: jon.fraser@broadcom.com Cc: pgynther@google.com Cc: paul.burton@imgtec.com Cc: ddaney.cavm@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12505/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
There are 2 distinct cases in which a kernel for a MIPS32 CPU (CONFIG_CPU_MIPS32=y) may use 64 bit physical addresses (CONFIG_PHYS_ADDR_T_64BIT=y): - 36 bit physical addressing as used by RMI Alchemy & Netlogic XLP/XLR CPUs. - MIPS32r5 eXtended Physical Addressing (XPA). These 2 cases are distinct in that they require different behaviour from the kernel - the EntryLo registers have different formats. Until Linux v4.1 we only supported the first case, with code conditional upon the 2 aforementioned Kconfig variables being set. Commit c5b36783 ("MIPS: Add support for XPA.") added support for the second case, but did so by modifying the code that existed for the first case rather than treating the 2 cases as distinct. Since the EntryLo registers have different formats this breaks the 36 bit Alchemy/XLP/XLR case. Fix this by splitting the 2 cases, with XPA cases now being conditional upon CONFIG_XPA and the non-XPA case matching the code as it existed prior to commit c5b36783 ("MIPS: Add support for XPA."). Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reported-by: NManuel Lauss <manuel.lauss@gmail.com> Tested-by: NManuel Lauss <manuel.lauss@gmail.com> Fixes: c5b36783 ("MIPS: Add support for XPA.") Cc: James Hogan <james.hogan@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Ingo Molnar <mingo@kernel.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: stable@vger.kernel.org # v4.1+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13119/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
The same definition for pte_page is duplicated for the MIPS32 PHYS_ADDR_T_64BIT case & the generic case. Unify them by moving a single definition outside of preprocessor conditionals. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13117/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
Ever since support for RI/XI was implemented by commit 6dd9344c ("MIPS: Implement Read Inhibit/eXecute Inhibit") we've had a mixture of _PAGE_READ & _PAGE_NO_READ bits. Rather than keep both around, switch away from using _PAGE_READ to determine page presence & instead invert the use to _PAGE_NO_READ. Wherever we formerly had no definition for _PAGE_NO_READ, change what was _PAGE_READ to _PAGE_NO_READ. The end result is that we consistently use _PAGE_NO_READ to determine whether a page is readable, regardless of whether RI/XI is implemented. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Cc: David Daney <david.daney@cavium.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13116/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
asm/pgtable-bits.h has grown to become an unreadable mess of #ifdef directives defining bits conditionally upon other bits all at the preprocessing stage, for no good reason. Instead of having quite so many #ifdef's, simply use enums to provide sequential numbering for bit shifts, without having to keep track manually of what the last bit defined was. Masks are defined separately, after the shifts, which allows for most of their definitions to be reused for all systems rather than duplicated. This patch is not intended to make any behavioural change to the code - all bits should be used in the same way they were before this patch. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13115/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
asm/pgtable-bits.h is included in 2 assembly files and thus has to ifdef around C code, however nothing defined by the header is used in either of the assembly files that include it. Remove the redundant inclusions such that asm/pgtable-bits.h doesn't need to #ifdef around C code, for cleanliness and in preparation for later patches which will add more C. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NJames Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13114/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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