This is a UIC cascade handler rework to use set_irq_chained_handler() for
cascade, just like othe ppc platforms do. With current implementation we have
additional redirection for irq handler and we call generic_handle_irq twice
(once for the primary uic and the other time for handling cascade interrupt).
This causes Ingo's realtime support patch to stop working on 4xx.

Not sure of any other possible problems though, but with
set_irq_chained_handler() we can abolish "struct irqaction cascade" from the
chip descriptor and call generic_handle_irq() once, directly for cascade irq.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This patch makes PowerPC 4xx UIC use generic level irq handler instead
of a custom handle_uic_irq() function. We ack only edge irqs in mask_ack
callback, since acking a level irq on UIC has no effect if the interrupt
is still asserted by the device, even if the interrupt is already masked.
So, to really de-assert the interrupt we need to de-assert the external
source first *and* ack it on UIC then. The handle_level_irq() function
masks and ack's the interrupt with mask_ack callback prior to calling
the actual ISR and unmasks it at the end. So, to use it with UIC interrupts
we need to ack level irqs in the unmask callback instead, after the ISR
has de-asserted the external interrupt source. Even if we ack the interrupt
that we didn't handle (unmask/ack it at the end of the handler, while
next irq is already pending) it will not de-assert the irq, untill we
de-assert its exteral source.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

PowerPC 440GRx Rainier default config.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

PowerPC 440GRx Rainier board support.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

PowerPC 440GRx Rainier DTS.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Bootwrapper code for PowerPC 440GRx Rainier board.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Add the 440EPx Sequoia USB OHCI device tree entry.
Signed-off-by: NValentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This makes 4xx embedded platforms re-assign all PCI resources as we
pretty much never care about what the various firmwares have done on
these, it's generally not compatible with the way the kernel will map
the bridges.

We still need to also enable bus renumbering on some of them, but I
will do that from a separate patch after I've fixed 4xx PCIe to handle
all bus numbers.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This improves the way the 4xx PCI-E code handles checking for a link
and adds explicit testing of CRS result codes on config space accesses.

This should make it more reliable.

Also, bridges with no link are now still created, though config space
accesses beyond the root complex are filtered. This is one step toward
eventually supporting hotplug.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This removes a bogus empty "ranges" property in the EBC device node
of the Bamboo board device-tree.

The "ranges" property should be created by the wrapper code when it is
implemented.  Until then, remove the empty property since it incorrectly
implies that there is a 1:1 address mapping between the EBC and the OPB.

This also fixes a warning from newer DTCs.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds base support for the Katmai board, including PCI-X and
PCI-Express (but no RTC, nvram, etc... yet).
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This reworks the boot wrapper library function that probes
the chip clocks. Better separate the base function that is
used on 440GX,SPe,EP,... from the uart fixups as those need
different device-tree path on different processors.

Also, rework the function itself based on the arch/ppc code
from Eugene Surovegin which I find more readable, and which
handles one more bypass case. Also handle the subtle difference
between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived
from the PLB clock while on the later, it's derived from the OPB.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds macros to the boot wrapper to access the CPR
registers from the boot wrappers.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

The 4xx bootwrapper occasionally needs to access SPR registers,
this adds mfspr/mtspr wrappers to it.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds a function to the bootwrapper 4xx library to decode memory
size on 440SPE processors.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds the definition of the on-chip OHCI controller to the
Bamboo board's device-tree. This is enough to get it probed and
working, though a separate patch fixing a bug in the OHCI driver
is needed to make it reliable.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds the device-tree bits & call to ppc4xx_pci_find_bridges()
to make PCI work on the Bamboo board
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This patch adds base support for the AMCC Taishan 440GX evaluation
board.
Signed-off-by: NHugh Blemings <hugh@blemings.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This wires up the 4xx PCI support & device-tree bits for the
405GP based Walnut platform.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD
comes from a device-tree property, PCI is working to the point where
I can see the video card, USB device, and south bridge.

This should work with both EP405 and EP405PC.

I've not totally figured out how IRQs are wired on this hardware
though, thus at this stage, expect only USB interrupts working,
pretty much the same as what arch/ppc did.

Also, the flash, nvram, rtc and temp control still have to be wired.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds some basic real mode based early udbg support for 40x
in order to debug things more easily
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This wires up the 4xx PCI support & device tree bits for
440GP based Ebony platform.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds to the previous 2 patches the support for the 4xx PCI Express
cells as found in the 440SPe revA, revB and 405EX.

Unfortunately, due to significant differences between these, and other
interesting "features" of those pieces of HW, the code isn't as simple
as it is for PCI and PCI-X and some of the functions differ significantly
between the 3 implementations. Thus, not only this code can only support
those 3 implementations for now and will refuse to operate on any other,
but there are added ifdef's to avoid the bloat of building a fairly large
amount of code on platforms that don't need it.

Also, this code currently only supports fully initializing root complex
nodes, not endpoint. Some more code will have to be lifted from the
arch/ppc implementation to add the endpoint support, though it's mostly
differences in memory mapping, and the question on how to represent
endpoint mode PCI in the device-tree is thus open.

Many thanks to Stefan Roese for testing & fixing up the 405EX bits !
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds to the previous patch the support for the 4xx PCI 2.x
bridges.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds base support code for the 4xx PCI-X bridge. It also provides
placeholders for the PCI and PCI-E version but they aren't supported
with this patch.

The bridges are configured based on device-tree properties.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Accessing indirect DCRs is done via a pair of address/data DCRs.

Such accesses are thus inherently racy, vs. interrupts, preemption
and possibly SMP if 4xx SMP cores are ever used.

This updates the mfdcri/mtdcri macros in dcr-native.h (which were
so far unused) to use a spinlock.

In addition, add some common definitions to a new dcr-regs.h file.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

This adds a cputable function pointer for the CPU-side machine
check handling. The semantic is still the same as the old one,
the one in ppc_md. overrides the one in cputable, though
ultimately we'll want to change that so the CPU gets first.

This removes CONFIG_440A which was a problem for multiplatform
kernels and instead fixes up the IVOR at runtime from a setup_cpu
function. The "A" version of the machine check also tweaks the
regs->trap value to differenciate the 2 versions at the C level.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>

Maple and pasemi both require PCI as does CONFIG_OF_PLATFORM_PCI.
The default setting of CONFIG_ISA_DMA_API is set to match the protection
around the relevant routines in asm/dma.h.

I also had to remove the PMAC platform from the combined build.  The
precis is that to build a 64 bit kernel with no PCI, you can only include
pSeries and iSeries.
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Fixes this warning:

arch/powerpc/platforms/powermac/pci.c: In function 'u3_ht_cfg_access':
arch/powerpc/platforms/powermac/pci.c:354: warning: return discards qualifiers from pointer target type
arch/powerpc/platforms/powermac/pci.c:358: warning: return discards qualifiers from pointer target type
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This will allow us to declare const all the statically declared arrrays
of these.
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

The 32-bit PCI code tests if "bus" is non-NULL after calling
pci_scan_bus_parented() in one place but not another before
dereferencing it.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This fixes a few issues with via-pmu based backlight control.

First, it fixes a sign problem with the setup of the backlight
curve since the `range' value there -can- (and will) go negative.

Then, it reworks the interaction between this and the via-pmu sleep
code to properly restore backlight on wakeup from sleep.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

These hooks ensure that a decrementer interrupt is not pending when
suspending; otherwise, problems may occur on 6xx/7xx/7xxx-based
systems (except for powermacs, which use a separate suspend path).
For example, with deep sleep on the 831x, a pending decrementer will
cause a system freeze because the SoC thinks the decrementer interrupt
would have woken the system, but the core must have interrupts
disabled due to the setup required for deep sleep.

Changed via-pmu.c to use the new ppc_md hooks, and made the arch_*
functions call the generic_* functions unconditionally.  -- paulus
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

Based on an original patch from Arnd Bergmann
<arnd.bergmann@de.ibm.com>

If there's no entry in the mailbox, then a read on the _info file will
return data from an uninitialised variable.

This change returns EOF if there's no mailbox info available instead.
Signed-off-by: NJeremy Kerr <jk@ozlabs.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

This fixes the behavior of spufs when a spu tries a DMA operation
based on a wrong / unavailable address.

Instead of just generating a SIGBUS signal, spufs now
generates a SIGSEGV signal and restarts the problematic DMA operation
after the execution of the application's signal handler.  This allows
applications to employ user-level paging systems.

Although the restart_dma function is called before the application's
signal handler, the operation is not actually performed at this time,
since the spu context is already stopped.  The operation only takes
place when spu_run is restarted (which happens automatically).
Signed-off-by: NAndre Detsch <adetsch@br.ibm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NJeremy Kerr <jk@ozlabs.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>

The original spusched_timer was designed to take effect only when
a context is waiting in the runqueue.

This change adds an additional lower-freq timer has been added to
purely handle the spu_load updates. The new timer will be triggered
per LOAD_FREQ ticks.
Signed-off-by: NAegis Lin <aegislin@gmail.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NJeremy Kerr <jk@ozlabs.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>