Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: arnd@arndb.de
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: bruherrera@gmail.com
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: lee.jones@linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1474387259-18926-5-git-send-email-alexandre.torgue@st.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Add Ethernet support (Synopsys MAC IP 3.50a) on stm32f429 SOC.
Signed-off-by: NAlexandre TORGUE <alexandre.torgue@gmail.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

Signed-off-by: NAlexandre TORGUE <alexandre.torgue@gmail.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

This patch adds USB HS support in host mode only.
This port supports OTG mode, but the device more is not working
properly as of now.
Once the device mode fixed, the node will be updated to support OTG.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

All the clocks referenced by the GPIO banks were not the good ones.
Reported-by: NBruno Herrera <bruherrera@gmail.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

STM32F429 allows to remap FMC SDRAM Bank 1 from 0xc0000000 to 0x0,
by writing 0x4 to SYSCFG_MEMRMP register.

As mentionned in the reference manual (see chapter 9.3.1), the performance
gain is really interresting:
"In remap mode at address 0x0000 0000, the CPU can access the external
memory via ICode bus instead of System bus which boosts up the
performance."

These are the dhrystone results with and without the remap enabled:
Default (SDRAM in 0xc0000000):
---------------------------------
Microseconds for one run through Dhrystone:   31.8
Dhrystones per Second:                      31416.9

Remap (SDRAM in 0x0000000):
-----------------------------
Microseconds for one run through Dhrystone:   20.6
Dhrystones per Second:                      48520.1

This patch first change the SDRAM start address to 0x0 for STM32429i-EVAL
board, and also set the dma-range property as the other masters than the M4
CPU still see SDRAM in 0xc0000000.

Note that the Discovery board cannot benefit from this feature, since the
SDRAM is connected to Bank 2.
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

This patch selects USART1 pin configuration on PA9/PA10 pins
for both Eval and Disco boards.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank.
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

This patch adds STM32 DMA bindings for STM32F429.
Signed-off-by: NM'boumba Cedric Madianga <cedric.madianga@gmail.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

New bindings and driver have been created for STM32 series parts. This
patch integrates this changes.
Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org>
Acked-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

New bindings and driver have been created for STM32F42xxx series parts.
This patch integrates these changes.

Note: Earlier device tree blobs (those without st,stm32f42xxx
      compatibles for the rcc) could still be used to boot basic
      systems. Such systems rely on the bootloader to configure the
      clock gates for vital periperhals.
Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org>
Reviewed-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>

The STMicrolectornics's STM32F429 MCU has the following main features:
 - Cortex-M4 core running up to @180MHz
 - 2MB internal flash, 256KBytes internal RAM
 - FMC controller to connect SDRAM, NOR and NAND memories
 - SD/MMC/SDIO support
 - Ethernet controller
 - USB OTFG FS & HS controllers
 - I2C, SPI, CAN busses support
 - Several 16 & 32 bits general purpose timers
 - Serial Audio interface
 - LCD controller
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>