The delay loops for reset and clock enable always take at least 1 ms
because they use mdelay(1). However they can take a lot less time e.g. less
than 50us. Use ktime and reduce the delay to 10 microseconds per loop.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Tested-by: NLudovic Desroches <ludovic.desroches@microchip.com>

The 2835 has two SD controllers: The Arasan sdhci controller (supported
by the iproc driver) and a custom sdhost controller.  This patch adds a
driver for the latter.

The sdhci controller supports both sdcard and sdio.  The sdhost
controller supports the sdcard only, but has better performance.  Also
note that the rpi3 has sdio wifi, so driving the sdcard with the sdhost
controller allows to use the sdhci controller for wifi support.

The configuration is done by devicetree via pin muxing.  Both SD
controller are available on the same pins (2 pin groups = pin 22 to 27 +
pin 48 to 53).  So it's possible to use both SD controllers at the same
time with different pin groups.

The code was originally written by Phil Elwell in the downstream
Rasbperry Pi tree.   In preparation for the upstream merge it was
cleaned up and the code base was moderized by Eric Anholt, Stefan
Wahren and Gerd Hoffmann.
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

File contains multiple functions doing variations on the same thing,
sdio_readb(), sdio_writeb()f, sdio_readw(), sdio_writew()
etc. Although the functions have very similar logic the code is laid
out in a variety of ways. This makes it overly complicated to
read. There is a already a nice clean chunk of code, if we use this
format for all instances then we will have cleaned up the code,
reduced the line count and lessened the cognitive load required while
reading. Less lines equals less bugs.

Pick the most simple and clear code flow and change all functions to
be the same.
Signed-off-by: NTobin C. Harding <me@tobin.cc>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Various functions take as parameter an optional pointer. Pointer
should be guarded with non-NULL check before dereferencing.

Add non-NULL check before dereference of pointer.
Signed-off-by: NTobin C. Harding <me@tobin.cc>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch fixes the case where meson_mmc_probe function fails before
core_clk is enabled.
Originally, that would result in a try to disable the core clock, and if
it was not already enabled, it would result in a kernel warning.
This issue is similar to the one with div_clk.
Fix it by introducing another error path used only between successfully
enabling the core clock, and successfully enabling the div clock.
That would ensure that core clock is disabled only if it was enabled before.
Signed-off-by: NMichał Zegan <webczat@webczatnet.pl>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhci_pltfm_init() has already set the platform drvdata for us, remove
the unnecessary platform_set_drvdata() call.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhci_pltfm_init() has already set the platform drvdata for us, remove
the unnecessary platform_set_drvdata() call.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

sdhci_pltfm_init() has already set the platform drvdata for us, remove
the unnecessary platform_set_drvdata() call.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Add support for HS400ES mode to Cadence SDHCI driver.
Signed-off-by: NPiotr Sroka <piotrs@cadence.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The SDHCI controller found on NVIDIA Tegra186 SoCs is very similar to
the one on prior generations of Tegra and can be supported by the same
driver.
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The device tree binding for the SDHCI controller found on Tegra SoCs
specifies that a reset control can be provided by the device tree. No
code was ever added to support the module reset, which can cause the
driver to try and access registers from a module that's in reset. On
most Tegra SoC generations doing so would cause a hang.

Note that it's unlikely to see this happen because on most platforms
these resets will have been deasserted by the bootloader. However the
portability can be improved by making sure the driver deasserts the
reset before accessing any registers.

Since resets are synchronous on Tegra SoCs, the platform driver needs
to implement a custom ->remove() callback now to make sure the clock
is disabled after the reset is asserted.
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The mmc host was added in meson_mmc_probe, but never removed in
meson_mmc_remove.
Fix that by removing the host before deallocating other resources.
Signed-off-by: NMichał Zegan <webczat@webczatnet.pl>
Tested-by: NMichał Zegan <webczat@webczatnet.pl>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

After we received the dataend interrupt, R1 response register carries
the value from the automatically generated stop command. Report that
info back to the MMC block layer, so we will be notified in case of e.g.
ECC errors which happened during the last transfer.
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Tested-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Halting the kernel on an unsupported stop command seems overkill, report
the error and say what we already did (due to autocmd12) instead.
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Making sure we match the actual register names.
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The current code assumes that DMA is finished before SD access end is
flagged. Thus, it schedules the 'dma_complete' tasklet in the SD card
interrupt routine when DATAEND is set. The assumption is not safe,
though. Even by mounting an SD card, it can be seen that sometimes DMA
complete is first, sometimes DATAEND. It seems they are usually close
enough timewise to not cause problems. However, a customer reported that
with CMD53 sometimes things really break apart. As a result, the BSP has
a patch which introduces flags for both events and makes sure both flags
are set before scheduling the tasklet. The customer accepted the patch,
yet it doesn't seem a proper upstream solution to me.

This patch refactors the code to replace the tasklet with already
existing and more lightweight mechanisms. First of all, we set the
callback in a DMA descriptor to automatically get notified when DMA is
done. In the callback, we then use a completion to make sure the SD
access has already ended. Then, we proceed as before.
Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

There is no check if clk_prepare_enable() succeed in sdhci_pxav2_probe().

Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: NAlexey Khoroshilov <khoroshilov@ispras.ru>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Replace timeout magic numbers with proper constants.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Struct mmc_command includes a reference to the related mmc_request.
Therefore we don't have to store mrq separately in struct meson_host.
And we can remove some now unneeded WARN_ON's.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Config values which are not changed during runtime we can set
in the probe function already.
The block size setting is overwritten later in
meson_mmc_start_cmd anyway if needed, so it doesn't harm if we
remove this setting in meson_mmc_set_ios.

In addition write config register only if configuration changed.

Don't change the location of clock initialization as in an
earlier version of the patch, this change causes a hang.
This issue was reported and fix suggested by:
Helmut Klein <hgkr.klein@gmail.com>
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

CLK core does a deep copy of init.name, therefore it's fully ok to
provide a local variable.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The condition should be "if (ret)" as the disable/unprepare is
supposed to be executed if the previous command fails.
In addition adjust the error path in probe to properly deal
with the case that cfg_div_clk can be registered successfully
but enable/prepare fails.
In this case we shouldn't call clk_disable_unprepare.
Reported-by: NMichał Zegan <webczat_200@poczta.onet.pl>
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Member mux_parent isn't used outside meson_mmc_clk_init. So remove it
and replace it with a local variable in meson_mmc_clk_init.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Because the DT requires a fixed number of mux parent clocks,
variable mux_parent_count can be replaced with constant
MUX_CLK_NUM_PARENTS, so remove it.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Member ocr_mask is never used and member irq we can replace with a
local variable in meson_mmc_probe. So let's remove both members.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The return value of meson_mmc_request_done and meson_mmc_read_resp
isn't used, so make both functions return void.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Core ensures that there are no commands with cmd->data being set and
nothing to transfer. And we don't have to reset bit CMD_CFG_DATA_NUM
because cmd_cfg was zero-initialized and this bit isn't set.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Too much condition iteration makes the code
less readable. Slightly improve it.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

No functional change intended.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

No need to declar it there, remove it.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

No functional change intended.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

No functional change intended.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

No functional change intended.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Just use the readl_poll_timeout{_atomic} to avold open
coding them.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Currently for DDR50 card, it need tuning in default. We meet tuning fail
issue for DDR50 card and some data CRC error when DDR50 sd card works.

This is because the default pad I/O drive strength can't make sure DDR50
card work stable. So increase the pad I/O drive strength for DDR50 card,
and use pins_100mhz.

This fixes DDR50 card support for IMX since DDR50 tuning was enabled from
commit 9faac7b9 ("mmc: sdhci: enable tuning for DDR50")
Tested-and-reported-by: NTim Harvey <tharvey@gateworks.com>
Signed-off-by: NHaibo Chen <haibo.chen@nxp.com>
Cc: stable@vger.kernel.org # v4.4+
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

According to the SDIO standard interrupts are normally signalled in a
very complicated way.  They require the card clock to be running and
require the controller to be paying close attention to the signals
coming from the card.  This simply can't happen with the clock stopped
or with the controller in a low power mode.

To that end, we'll disable runtime_pm when we detect that an SDIO card
was inserted.  This is much like with what we do with the special
"SDMMC_CLKEN_LOW_PWR" bit that dw_mmc supports.

NOTE: we specifically do this Runtime PM disabling at card init time
rather than in the enable_sdio_irq() callback.  This is _different_
than how SDHCI does it.  Why do we do it differently?

- Unlike SDHCI, dw_mmc uses the standard sdio_irq code in Linux (AKA
  dw_mmc doesn't set MMC_CAP2_SDIO_IRQ_NOTHREAD).
- Because we use the standard sdio_irq code:
  - We see a constant stream of enable_sdio_irq(0) and
    enable_sdio_irq(1) calls.  This is because the standard code
    disables interrupts while processing and re-enables them after.
  - While interrupts are disabled, there's technically a period where
    we could get runtime disabled while processing interrupts.
  - If we are runtime disabled while processing interrupts, we'll
    reset the controller at resume time (see dw_mci_runtime_resume),
    which seems like a terrible idea because we could possibly have
    another interrupt pending.

To fix the above isues we'd want to put something in the standard
sdio_irq code that makes sure to call pm_runtime get/put when
interrupts are being actively being processed.  That's possible to do,
but it seems like a more complicated mechanism when we really just
want the runtime pm disabled always for SDIO cards given that all the
other bits needed to get Runtime PM vs. SDIO just aren't there.

NOTE: at some point in time someone might come up with a fancy way to
do SDIO interrupts and still allow (some) amount of runtime PM.
Technically we could turn off the card clock if we used an alternate
way of signaling SDIO interrupts (and out of band interrupt is one way
to do this).  We probably wouldn't actually want to fully runtime
suspend in this case though--at least not with the current
dw_mci_runtime_resume() which basically fully resets the controller at
resume time.

Fixes: e9ed8835 ("mmc: dw_mmc: add runtime PM callback")
Cc: <stable@vger.kernel.org>
Reported-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Certain 64-bit systems (e.g. Amlogic Meson GX) require buffers to be
used for DMA to be 8-byte-aligned. struct sdio_func has an embedded
small DMA buffer not meeting this requirement.
When testing switching to descriptor chain mode in meson-gx driver
SDIO is broken therefore. Fix this by allocating the small DMA buffer
separately as kmalloc ensures that the returned memory area is
properly aligned for every basic data type.
Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
Tested-by: NHelmut Klein <hgkr.klein@gmail.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

The controller has different timings for MMC_TIMING_UHS_DDR50 and
MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
when MMC_TIMING_MMC_DDR52 timings are requested, is not correct and can
lead to unexpected behavior.
Signed-off-by: NLudovic Desroches <ludovic.desroches@microchip.com>
Fixes: bb5f8ea4 ("mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC")
Cc: <stable@vger.kernel.org> # 4.4+
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

SDIO cards may need clock to send the card interrupt to the host.

On a cherrytrail tablet with a RTL8723BS wifi chip, without this patch
pinging the tablet results in:

PING 192.168.1.14 (192.168.1.14) 56(84) bytes of data.
64 bytes from 192.168.1.14: icmp_seq=1 ttl=64 time=78.6 ms
64 bytes from 192.168.1.14: icmp_seq=2 ttl=64 time=1760 ms
64 bytes from 192.168.1.14: icmp_seq=3 ttl=64 time=753 ms
64 bytes from 192.168.1.14: icmp_seq=4 ttl=64 time=3.88 ms
64 bytes from 192.168.1.14: icmp_seq=5 ttl=64 time=795 ms
64 bytes from 192.168.1.14: icmp_seq=6 ttl=64 time=1841 ms
64 bytes from 192.168.1.14: icmp_seq=7 ttl=64 time=810 ms
64 bytes from 192.168.1.14: icmp_seq=8 ttl=64 time=1860 ms
64 bytes from 192.168.1.14: icmp_seq=9 ttl=64 time=812 ms
64 bytes from 192.168.1.14: icmp_seq=10 ttl=64 time=48.6 ms

Where as with this patch I get:

PING 192.168.1.14 (192.168.1.14) 56(84) bytes of data.
64 bytes from 192.168.1.14: icmp_seq=1 ttl=64 time=3.96 ms
64 bytes from 192.168.1.14: icmp_seq=2 ttl=64 time=1.97 ms
64 bytes from 192.168.1.14: icmp_seq=3 ttl=64 time=17.2 ms
64 bytes from 192.168.1.14: icmp_seq=4 ttl=64 time=2.46 ms
64 bytes from 192.168.1.14: icmp_seq=5 ttl=64 time=2.83 ms
64 bytes from 192.168.1.14: icmp_seq=6 ttl=64 time=1.40 ms
64 bytes from 192.168.1.14: icmp_seq=7 ttl=64 time=2.10 ms
64 bytes from 192.168.1.14: icmp_seq=8 ttl=64 time=1.40 ms
64 bytes from 192.168.1.14: icmp_seq=9 ttl=64 time=2.04 ms
64 bytes from 192.168.1.14: icmp_seq=10 ttl=64 time=1.40 ms

Cc: Dong Aisheng <b29396@freescale.com>
Cc: Ian W MORRISON <ianwmorrison@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Cc: stable@vger.kernel.org
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>