1. 18 8月, 2014 2 次提交
    • S
      ARM: imx: fix TLB missing of IOMUXC base address during suspend · 59d05b51
      Shawn Guo 提交于
      After the suspend routine running in OCRAM puts DDR into self-refresh,
      it will access IOMUXC block to float DDR IO for power saving.  A TLB
      missing of IOMUXC base address may happen in this case, and triggers an
      access to DDR, and thus hangs the system.
      
      The failure is discovered by running suspend/resume on a Cubox-i board.
      Though the issue is not Cubox-i specific, it can be hit the on the board
      quite easily with the 3.15 or 3.16 kernel.
      
      Fix the issue with a dummy access to IOMUXC block at the beginning of
      suspend routine, so that the address translation can be filled into TLB
      before DDR is put into self-refresh.
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      Cc: <stable@vger.kernel.org>
      Acked-by: NAnson Huang <Anson.Huang@freescale.com>
      59d05b51
    • A
      ARM: imx6: fix SMP compilation again · 060d517d
      Arnd Bergmann 提交于
      My earlier patch 1fc593fe ("ARM: imx: build i.MX6 functions
      only when needed") fixed a problem with building an i.MX5 kernel,
      but now the problem has returned for the case where we allow
      ARMv6K SMP builds in multiplatform. With CONFIG_CPU_V7 disabled,
      but i.MX3 and SMP enabled, we get this build error:
      
      arch/arm/mach-imx/built-in.o: In function `v7_secondary_startup':
      :(.text+0x5124): undefined reference to `v7_invalidate_l1'
      
      This puts the code inside of an "ifdef CONFIG_SOC_IMX6" to hopefully
      do the right thing in all configurations.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
      060d517d
  2. 17 8月, 2014 1 次提交
  3. 16 8月, 2014 37 次提交