1. 04 4月, 2012 3 次提交
    • I
      ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases · 59269b94
      Ilya Yanok 提交于
      Rename EMAC clocks to match driver expectations: both davinci_emac and
      davinci_mdio drivers call clk_get(dev, NULL) so we have to provide
      ("davinci_emac", NULL) and ("davinci_mdio.0", NULL) clocks instead of
      ("davinci_emac", "emac_clk") and ("davinci_emac", "phy_clk") resp.
      
      Cc: Paul Walmsley <paul@pwsan.com>
      Signed-off-by: NIlya Yanok <yanok@emcraft.com>
      Tested-by: NYegor Yefremov <yegorslists@googlemail.com>
      Tested-by: NMatt Porter <mporter@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      59269b94
    • N
      ARM: OMAP: clock: fix race in disable all clocks · 0eb4fd9b
      Nishanth Menon 提交于
      clk_disable_unused is invoked when CONFIG_OMAP_RESET_CLOCKS=y.
      Since clk_disable_unused is called as lateinitcall, there can
      be more than a few workqueues executing off secondary CPU(s).
      The current code does the following:
      a) checks if clk is unused
      b) holds lock
      c) disables clk
      d) unlocks
      
      Between (a) and (b) being executed on CPU0, It is possible to
      have a driver executing on CPU1 which could do a get_sync->clk_get
      (and increase the use_count) of the clock which was just about
      to be disabled by clk_disable_unused.
      
      We ensure instead that the entire list traversal is protected by
      the lock allowing for parent child clock traversal which could be
      potentially be done by runtime operations to be safe as well.
      Reported-by: NTodd Poynor <toddpoynor@google.com>
      Signed-off-by: NNishanth Menon <nm@ti.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      0eb4fd9b
    • G
      ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks · ac387330
      Grazvydas Ignotas 提交于
      Commit 2a9f5a4d "OMAP3 clock: remove unnecessary duplicate of dpll4_m2_ck,
      added for 36xx" consolidated dpll4 clock structures between 34xx and 36xx,
      but left 34xx CLKSEL masks for most dpll4 related clocks, which causes
      clock code to not behave correctly when booting on DM3730 with higher
      (36xx only) divisors set:
      [    0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:375 omap2_init_clksel_parent+0x104/0x114()
      [    0.000000] clock: dpll4_m3_ck: init parent: could not find regval 0
      [    0.000000] WARNING: at arch/arm/mach-omap2/clkt_clksel.c:194 omap2_clksel_recalc+0xd4/0xe4()
      [    0.000000] clock: Could not find fieldval 0 for clock dpll4_m3_ck parent dpll4_ck
      
      Fix this by switching to 36xx masks, as valid divisors will be limited
      by clksel_rate lists.
      
      Cc: Paul Walmsley <paul@pwsan.com>
      Signed-off-by: NGrazvydas Ignotas <notasas@gmail.com>
      Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      ac387330
  2. 01 4月, 2012 1 次提交
  3. 31 3月, 2012 4 次提交
  4. 30 3月, 2012 13 次提交
  5. 29 3月, 2012 19 次提交