1. 02 9月, 2020 2 次提交
    • R
      Intel: intel_idle: Use ACPI _CST for processor models without C-state tables · 5887563b
      Rafael J. Wysocki 提交于
      task #29239886
      
      commit 18734958e9bfbc055805d110a38dc76307eba742 upstream
      
      Modify the intel_idle driver to get the C-states information from ACPI
      _CST if the processor model is not recognized by it.
      
      The processor is still required to support MWAIT and the information
      from ACPI _CST will only be used if all of the C-states listed by
      _CST are of the ACPI_CSTATE_FFH type (which means that they are
      expected to be entered via MWAIT).
      
      Moreover, the driver assumes that the _CST information is the same
      for all CPUs in the system, so it is sufficient to evaluate _CST for
      one of them and extract the common list of C-states from there.
      Also _CST is evaluated once at the system initialization time and
      the driver does not respond to _CST change notifications (that can
      be changed in the future).
      
      The main functional difference between intel_idle with this change
      and the ACPI processor driver is that the former sets the target
      residency to be equal to the exit latency (provided by _CST) for
      C1-type C-states and to 3 times the exit latency value for the other
      C-state types, whereas the latter obtains the target residency by
      multiplying the exit latency by the same number (2 by default) for
      all C-state types.  Therefore it is expected that in general using
      the former instead of the latter on the same system will lead to
      improved energy-efficiency.
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Signed-off-by: Nyjia <yingbao.jia@intel.com>
      Signed-off-by: NErwei Deng <erwei@linux.alibaba.com>
      Reviewed-by: NArtie Ding <artie.ding@linux.alibaba.com>
      5887563b
    • R
      Intel: intel_idle: Refactor intel_idle_cpuidle_driver_init() · 7af3d4b5
      Rafael J. Wysocki 提交于
      task #29239886
      
      commit 9f3d6daf61e5156139cd05643f7f1c2a9b7b49b0 upstream
      
      Move the C-state verification and checks from
      intel_idle_cpuidle_driver_init() to a separate function,
      intel_idle_verify_cstate(), and make the former call it after
      checking the CPUIDLE_FLAG_UNUSABLE state flag.
      
      Also combine the drv->states[] updates with the incrementation of
      drv->state_count.
      
      No intentional functional impact.
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Signed-off-by: Nyjia <yingbao.jia@intel.com>
      Signed-off-by: NErwei Deng <erwei@linux.alibaba.com>
      Reviewed-by: NArtie Ding <artie.ding@linux.alibaba.com>
      7af3d4b5
  2. 15 5月, 2019 1 次提交
    • P
      x86/cpu: Sanitize FAM6_ATOM naming · 1f1bc822
      Peter Zijlstra 提交于
      commit f2c4db1bd80720cd8cb2a5aa220d9bc9f374f04e upstream
      
      Going primarily by:
      
        https://en.wikipedia.org/wiki/List_of_Intel_Atom_microprocessors
      
      with additional information gleaned from other related pages; notably:
      
       - Bonnell shrink was called Saltwell
       - Moorefield is the Merriefield refresh which makes it Airmont
      
      The general naming scheme is: FAM6_ATOM_UARCH_SOCTYPE
      
        for i in `git grep -l FAM6_ATOM` ; do
      	sed -i  -e 's/ATOM_PINEVIEW/ATOM_BONNELL/g'		\
      		-e 's/ATOM_LINCROFT/ATOM_BONNELL_MID/'		\
      		-e 's/ATOM_PENWELL/ATOM_SALTWELL_MID/g'		\
      		-e 's/ATOM_CLOVERVIEW/ATOM_SALTWELL_TABLET/g'	\
      		-e 's/ATOM_CEDARVIEW/ATOM_SALTWELL/g'		\
      		-e 's/ATOM_SILVERMONT1/ATOM_SILVERMONT/g'	\
      		-e 's/ATOM_SILVERMONT2/ATOM_SILVERMONT_X/g'	\
      		-e 's/ATOM_MERRIFIELD/ATOM_SILVERMONT_MID/g'	\
      		-e 's/ATOM_MOOREFIELD/ATOM_AIRMONT_MID/g'	\
      		-e 's/ATOM_DENVERTON/ATOM_GOLDMONT_X/g'		\
      		-e 's/ATOM_GEMINI_LAKE/ATOM_GOLDMONT_PLUS/g' ${i}
        done
      Signed-off-by: NPeter Zijlstra (Intel) <peterz@infradead.org>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Vince Weaver <vincent.weaver@maine.edu>
      Cc: dave.hansen@linux.intel.com
      Cc: len.brown@intel.com
      Signed-off-by: NIngo Molnar <mingo@kernel.org>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      1f1bc822
  3. 09 11月, 2017 1 次提交
  4. 04 11月, 2017 1 次提交
    • A
      Revert "x86/mm: Stop calling leave_mm() in idle code" · 67535736
      Andy Lutomirski 提交于
      This reverts commit 43858b4f.
      
      The reason I removed the leave_mm() calls in question is because the
      heuristic wasn't needed after that patch.  With the original version
      of my PCID series, we never flushed a "lazy cpu" (i.e. a CPU running
      kernel thread) due a flush on the loaded mm.
      
      Unfortunately, that caused architectural issues, so now I've
      reinstated these flushes on non-PCID systems in:
      
          commit b956575b ("x86/mm: Flush more aggressively in lazy TLB mode").
      
      That, in turn, gives us a power management and occasionally
      performance regression as compared to old kernels: a process that
      goes into a deep idle state on a given CPU and gets its mm flushed
      due to activity on a different CPU will wake the idle CPU.
      
      Reinstate the old ugly heuristic: if a CPU goes into ACPI C3 or an
      intel_idle state that is likely to cause a TLB flush gets its mm
      switched to init_mm before going idle.
      
      FWIW, this heuristic is lousy.  Whether we should change CR3 before
      idle isn't a good hint except insofar as the performance hit is a bit
      lower if the TLB is getting flushed by the idle code anyway.  What we
      really want to know is whether we anticipate being idle long enough
      that the mm is likely to be flushed before we wake up.  This is more a
      matter of the expected latency than the idle state that gets chosen.
      This heuristic also completely fails on systems that don't know
      whether the TLB will be flushed (e.g. AMD systems?).  OTOH it may be a
      bit obsolete anyway -- PCID systems don't presently benefit from this
      heuristic at all.
      
      We also shouldn't do this callback from innermost bit of the idle code
      due to the RCU nastiness it causes.  All the information need is
      available before rcu_idle_enter() needs to happen.
      Signed-off-by: NAndy Lutomirski <luto@kernel.org>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Borislav Petkov <bpetkov@suse.de>
      Cc: Brian Gerst <brgerst@gmail.com>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Josh Poimboeuf <jpoimboe@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Fixes: 43858b4f "x86/mm: Stop calling leave_mm() in idle code"
      Link: http://lkml.kernel.org/r/c513bbd4e653747213e05bc7062de000bf0202a5.1509793738.git.luto@kernel.orgSigned-off-by: NIngo Molnar <mingo@kernel.org>
      67535736
  5. 11 10月, 2017 1 次提交
  6. 30 8月, 2017 1 次提交
  7. 11 8月, 2017 1 次提交
  8. 05 7月, 2017 1 次提交
  9. 30 6月, 2017 1 次提交
  10. 02 5月, 2017 1 次提交
  11. 01 3月, 2017 2 次提交
  12. 02 12月, 2016 2 次提交
  13. 01 12月, 2016 2 次提交
  14. 08 10月, 2016 1 次提交
  15. 09 7月, 2016 2 次提交
  16. 01 7月, 2016 1 次提交
  17. 23 6月, 2016 2 次提交
    • J
      idle_intel: Add Denverton · 0080d65b
      Jacob Pan 提交于
      Denverton is an Intel Atom based micro server which shares the same
      Goldmont architecture as Broxton. The available C-states on
      Denverton is a subset of Broxton with only C1, C1e, and C6.
      Signed-off-by: NJacob Pan <jacob.jun.pan@linux.intel.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      0080d65b
    • P
      drivers/idle: make intel_idle.c driver more explicitly non-modular · 02c4fae9
      Paul Gortmaker 提交于
      The Kconfig for this driver is currently declared with:
      
      config INTEL_IDLE
              bool "Cpuidle Driver for Intel Processors"
      
      ...meaning that it currently is not being built as a module by anyone.
      
      This was done in commit 6ce9cd86
      ("intel_idle: disable module support") since "...the module capability
      is cauing more trouble than it is worth."
      
      This was done over 5y ago, and Daniel adds that:
      
          ...the modular support has been removed from almost all the cpuidle
          drivers and the cpuidle framework is no longer assuming driver could
          be unloaded.
      
          Removing the modular dead code in the driver makes sense as this
          what have been done in the others drivers.
      
      So lets remove the modular code that is essentially orphaned, so that
      when reading the driver there is no doubt it is builtin-only.
      
      Since module_init translates to device_initcall in the non-modular
      case, the init ordering remains unchanged with this commit.  At a
      later date we might want to consider whether subsys_init or another
      init category seems more appropriate than device_init.
      
      We replace module.h with moduleparam.h since the file does declare
      some module parameters, and leaving them as such is currently the
      easiest way to remain compatible with existing boot arg use cases.
      
      Note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
      
      Also note that we can't remove intel_idle_cpuidle_devices_uninit() as
      that is still used for unwind purposes if the init fails.
      
      We also delete the MODULE_LICENSE tag etc. since all that information
      is already contained at the top of the file in the comments.
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: NLen Brown <len.brown@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      02c4fae9
  18. 08 6月, 2016 1 次提交
    • D
      x86/intel_idle: Use Intel family macros for intel_idle · db73c5a8
      Dave Hansen 提交于
      Use the new INTEL_FAM6_* macros for intel_idle.c.  Also fix up
      some of the macros to be consistent with how some of the
      intel_idle code refers to the model.
      
      There's on oddity here: model 0x1F is uniquely referred to here
      and nowhere else that I could find.  0x1E/0x1F are just spelled
      out as "Intel Core i7 and i5 Processors" in the SDM or as "Intel
      processors based on the Nehalem, Westmere microarchitectures" in
      the RDPMC section.  Comments between tables 19-19 and 19-20 in
      the SDM seem to point to 0x1F being some kind of Westmere, so
      let's call it "WESTMERE2".
      Signed-off-by: NDave Hansen <dave.hansen@linux.intel.com>
      Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Brian Gerst <brgerst@gmail.com>
      Cc: Dave Hansen <dave@sr71.net>
      Cc: Denys Vlasenko <dvlasenk@redhat.com>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Len Brown <lenb@kernel.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: jacob.jun.pan@intel.com
      Cc: linux-pm@vger.kernel.org
      Link: http://lkml.kernel.org/r/20160603001932.EE978EB9@viggo.jf.intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      db73c5a8
  19. 09 4月, 2016 1 次提交
  20. 08 4月, 2016 12 次提交
  21. 24 3月, 2016 2 次提交
  22. 11 9月, 2015 1 次提交