Current pciehp driver creates 'attention' and 'latch' files even if
the controller doesn't support them. In this case, the contents of
those files are meaningless and unpredictable. Those files should be
created only if the controller has the corresponding capabilities.
Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Remove wrong workaround for BAD DLLP error, which confused surprise
down error with DLL errors.
Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Current pciehp doesn't handle Data Link Layer State Changed Event
notification. So it needs to be disabled at initialization time,
otherwise other event notifications are not generated.
Signed-off-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

When probing for ROM BAR size, we should not change bits 1:10 in this
BAR, because these bits are marked as "reserved for future use" in PCI
spec, so changing them might have side effects.

No such issue for I/O or memory, as there is an implementation note in
PCI spec which explicitly allows writing 0xfffffffff there.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

We use dev_dbg() in arch/x86/pci, but there's no easy way to turn it
on.  Add -DDEBUG when CONFIG_PCI_DEBUG=y, just like we do in drivers/pci.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This patch is predicated on Jeremy's patch in include/xen/xen.h.  It'll
prevent ACS init unless the platform has both an IOMMU and we're running
as dom0.
Signed-off-by: NAllen Kay <allen.m.kay@intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Note: dom0 checking in v4 has been separated out into 2/2.

This patch enables P2P upstream forwarding in ACS capable PCIe switches.
It solves two potential problems in virtualization environment where a PCIe
device is assigned to a guest domain using a HW iommu such as VT-d:

1) Unintentional failure caused by guest physical address programmed
   into the device's DMA that happens to match the memory address range
   of other downstream ports in the same PCIe switch.  This causes the PCI
   transaction to go to the matching downstream port instead of go to the
   root complex to get translated by VT-d as it should be.

2) Malicious guest software intentionally attacks another downstream
   PCIe device by programming the DMA address into the assigned device
   that matches memory address range of the downstream PCIe port.

We are in process of implementing device filtering software in KVM/XEN
management software to allow device assignment of PCIe devices behind a PCIe
switch only if it has ACS capability and with the P2P upstream forwarding bits
enabled.  This patch is intended to work for both KVM and Xen environments.
Signed-off-by: NAllen Kay <allen.m.kay@intel.com>
Reviewed-by: NMathew Wilcox <willy@linux.intel.com>
Reviewed-by: NChris Wright <chris@sous-sol.org>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Move xen_domain and related tests out of asm-x86 to xen/xen.h so they
can be included whenever they are necessary.
Signed-off-by: NJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

The current whitelist requires a kernel change for every machine that has
MMCONFIG regions above 4GB, even if BIOS provides a correct MCFG table.

This patch expands the whitelist to include machines with a rev 1 or newer
MCFG table and a DMI_BIOS_DATE of 2010 or later.  That way, we only need
kernel changes for new machines that provide incorrect MCFG tables.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
CC: Matthew Wilcox <willy@linux.intel.com>
CC: John Keller <jpk@sgi.com>
CC: Yinghai Lu <yhlu.kernel@gmail.com>
CC: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
CC: Andi Kleen <andi@firstfloor.org>
Acked-by: NIngo Molnar <mingo@elte.hu>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Thomas Schlichter reported:
> X.org uses libpciaccess which tries to mmap with write combining enabled via
> /sys/bus/pci/devices/*/resource0_wc. Currently, when PAT is not enabled, the
> kernel does fall back to uncached mmap. Then libpciaccess thinks it succeeded
> mapping with write combining enabled and does not set up suited MTRR entries.
> ;-(

Instead of silently mapping pci mmap region as UC minus in the case
of !pat_enabled and wc request, we can return error. Eric Anholt mentioned
that caller (like X) typically follows up with UC minus pci mmap request and
if there is a free mtrr slot, caller will manage adding WC mtrr.

Jesse Barnes says:
> Older versions of libpciaccess will behave better if we do it that way
> (iirc it only allocates an MTRR if the resource_wc file doesn't exist or
> fails to get mapped).
Reported-by: NThomas Schlichter <thomas.schlichter@web.de>
Signed-off-by: NThomas Schlichter <thomas.schlichter@web.de>
Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
Acked-by: NEric Anholt <eric@anholt.net>
Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This uses %pRt and %pRf to print additional resource information (type,
size, prefetchability, etc.) consistently.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This uses %pRt to print additional resource information (type, size,
prefetchability, etc.) consistently.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This uses %pRt to print additional resource information (type, size,
prefetchability, etc.) consistently.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This uses %pRt to print additional resource information (type, size,
prefetchability, etc.) consistently.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

This adds support for printing struct resource type and flag information.
For example, "%pRt" looks like "[mem 0x80080000000-0x8008001ffff 64bit pref]",
and "%pRf" looks like "[mem 0xff5e2000-0xff5e2007 pref flags 0x1]".
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Print addresses (IO port numbers and memory addresses) in hex, but print
others (IRQs and DMA channels) in decimal.  Only print the end if it's
different from the start.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

The leading "0x" consumes field width, so leave space for it in addition to
the 4 or 8 hex digits.  This means we'll print "0x0000-0x01df" rather than
"0x00-0x1df", for example.
Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

As a followup to 71a082ef, it's conceivable
that some vendors may expose PCI hotplug functionality through both vendor
mechanisms and ACPI. The native mechanism will generally be a superset of
any functionality provided via ACPI, so the acpiphp driver should always
be initialised after any others. Change the link order such that acpiphp
will not be initialised until any other statically linked drivers have had
an opportunity to claim the hardware.
Signed-off-by: NMatthew Garrett <mjg@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Change PCI nomenclature according to
http://www.pcisig.com/developers/procedures/logos/Trademark_and_Logo_Usage_Guidelines_updated_112206.pdf.
Signed-off-by: NStefan Assmann <sassmann@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Instead of the PCI code needing to have code to determine the
cacheline size of each processor, use the data the cpu identification
code should have already determined during early boot.

(The vendor checks are also incomplete, and don't take into account
 modern CPUs)

I've been carrying a variant of this code in Fedora for a while,
that prints debug information.  There are a number of cases where we
are currently setting the PCI cacheline size to 32 bytes, when the CPU
cacheline size is 64 bytes.  With this patch, we set them both the same.
Signed-off-by: NDave Jones <davej@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

pci_dfl_cache_line_size is marked as __initdata but referenced by
pci_init() which is __devinit.  Make it __devinitdata instead of
__initdata.
Signed-off-by: NTejun Heo <tj@kernel.org>
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

For non hotplug PCI devices, the system firmware usually configures
CLS correctly.  For pccard devices system firmware can't do it and
Linux PCI layer doesn't do it either.  Unfortunately this leads to
poor performance for certain devices (sata_sil).  Unless MWI, which
requires separate configuration, is to be used, CLS doesn't affect
correctness, so the configuration should be harmless.

This patch makes pci_set_cacheline_size() always built and export it
and make pccard call it during attach.

Please note that some other PCI hotplug drivers (shpchp and pciehp)
also configure CLS on hotplug.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Daniel Ritz <daniel.ritz@gmx.ch>
Cc: Dominik Brodowski <linux@dominikbrodowski.net>
Cc: Greg KH <greg@kroah.com>
Cc: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Cc: Axel Birndt <towerlexa@gmx.de>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

sparc64 is now the only user of PCI_CACHE_LINE_BYTES.  Drop it and set
pci_dfl_cache_line_size from pcibios_init() instead and drop
PCI_CACHE_LINE_BYTES handling from generic pci code.

Orignally-From: David Miller <davem@davemloft.net>
Signed-off-by: NTejun Heo <tj@kernel.org>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Till now, CLS has been determined either by arch code or as
L1_CACHE_BYTES.  Only x86 and ia64 set CLS explicitly and x86 doesn't
always get it right.  On most configurations, the chance is that
firmware configures the correct value during boot.

This patch makes pci_init() determine CLS by looking at what firmware
has configured.  It scans all devices and if all non-zero values
agree, the value is used.  If none is configured or there is a
disagreement, pci_dfl_cache_line_size is used.  arch can set the dfl
value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or
override the actual one.

ia64, x86 and sparc64 updated to set the default cls instead of the
actual one.

While at it, declare pci_cache_line_size and pci_dfl_cache_line_size
in pci.h and drop private declarations from arch code.
Signed-off-by: NTejun Heo <tj@kernel.org>
Acked-by: NDavid Miller <davem@davemloft.net>
Acked-by: NGreg KH <gregkh@suse.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

For intel systems with multi IOH, we should read peer root resources
directly from PCI config space, and don't trust _CRS.
Signed-off-by: NYinghai Lu <yinghai.lu@sun.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: Ironlake suspend/resume support
  drm/i915: kill warning in intel_find_pll_g4x_dp
  drm/i915: update watermarks before enabling PLLs
  drm/i915: add FIFO watermark support for G4x
  drm/i915: quiet DP i2c init
  drm/i915: fix panel fitting filter coefficient select for Ironlake
  drm/i915: fix to setup display reference clock control on Ironlake
  drm/i915: Install a fence register for fbc on g4x
  drm/i915: save/restore BLC histogram control reg across suspend/resume
  drm/i915: Fix FDI M/N setting according with correct color depth
  drm/i915: disable powersave feature for Ironlake currently
  drm/i915: Fix render reclock availability detection.
  drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
  drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
  drm/i915: disable FBC for Pineview, fixing a boot hang.

* 'for-linus' of git://git.kernel.dk/linux-2.6-block:
  cfq-iosched: limit coop preemption
  cfq-iosched: fix bad return value cfq_should_preempt()
  backing-dev: bdi sb prune should be in the unregister path, not destroy
  Fix bio_alloc() and bio_kmalloc() documentation
  bio_put(): add bio_clone() to the list of functions in the comment

* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
  sata_via: Remove redundant device ID for VIA VT8261
  drivers/ata/libata: Move dereference after NULL test
  ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2

Just remove redundant device ID for VIA VT8261.
The device ID 0x9000 and 0x9040 are redundant (for VT8261).
The 0x9040 is reserved for other usage.
Signed-off-by: NJoseph Chan <josephchan@via.com.tw>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

In each case, if the NULL test on qc is needed, then the derefernce
should be after the NULL test.

A simplified version of the semantic match that detects this problem is as
follows (http://coccinelle.lip6.fr/):

// <smpl>
@match exists@
expression x, E;
identifier fld;
@@

* x->fld
  ... when != \(x = E\|&x\)
* x == NULL
// </smpl>
Signed-off-by: NJulia Lawall <julia@diku.dk>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

Like the Asus M2A-VM, MSI's K9A2 Platinum (MS-7376) can also support 64bit
DMA. It is a new enough board that all the BIOS releases work correctly with
64bit DMA enabled.
Signed-off-by: NMark Nelson <mdnelson8@gmail.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

CFQ has an optimization for cooperated applications. if several
io-context have close requests, they will get boost. But the
optimization get abused. Considering thread a, b, which work on one
file. a reads sectors s, s+2, s+4, ...; b reads sectors s+1, s+3, s
+5, ... Both a and b are sequential read, so they can open idle window.
a reads a sector s and goes to idle window and wakeup b. b reads sector
s+1, since in current implementation, cfq_should_preempt() thinks a and
b are cooperators, b will preempt a. b then reads sector s+1 and goes to
idle window and wakeup a. for the same reason, a will preempt b and
reads s+2. a and b will continue the circle. The circle will be very
long, and a and b will occupy whole disk queue. Other applications will
nearly have no chance to run.

Fix this limiting coop preempt until a queue is scheduled normally
again.
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Acked-by: NJeff Moyer <jmoyer@redhat.com>
Signed-off-by: NJens Axboe <jens.axboe@oracle.com>

Commit a6151c3a inadvertently reversed
a preempt condition check, potentially causing a performance regression.
Make the meta check correct again.
Signed-off-by: NJens Axboe <jens.axboe@oracle.com>

Commit 592b09a4 was different from
the tested path, in that it moved the bdi super_block prune from
unregister to destroy context. This doesn't fully fix the sync hang
bug on unexpected device removal, as need to prune the bdi cache
pointer before killing flusher thread.
Tested-by: NArtur Skawina <art.08.09@gmail.com>
Signed-off-by: NJens Axboe <jens.axboe@oracle.com>

* 'for-linus' of git://github.com/at91linux/linux-2.6-at91:
  at91: at91sam9g45 family: identify several chip versions
  avr32: add two new at91 to cpu.h definition

cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds
the capacity to differentiate Engineering Samples and final lots through the
inclusion of  at91_cpu_fully_identify() and the related chip IDs with chip
version field preserved.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NHans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>

Somme common drivers will need those at91 cpu_is_xxx() definitions. As
at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch
that adds those chips to cpu.h in AVR32 architecture.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com>

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
  MIPS: O32: Fix ppoll
  MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
  MIPS: Alchemy: Fix hang with high-frequency edge interrupts
  MIPS: TXx9: Fix spi-baseclk value
  MIPS: bcm63xx: Set the correct BCM3302 CPU name
  MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
  MIPS: Avoid potential hazard on Context register
  MIPS: Octeon: Use lockless interrupt controller operations when possible.
  MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
  MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
  MIPS: SMTC: Avoid queing multiple reschedule IPIs
  MIPS: GCMP: Avoid accessing registers when they are not present
  MIPS: GIC: Random fixes and enhancements.
  MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
  MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
  MIPS: SPRAM: Clean up support code a little
  MIPS: 1004K: Enable SPRAM support.
  MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
  MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
  MIPS: MTI: Fix accesses to device registers on MIPS boards
  ...

* 'pm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/suspend-2.6:
  PM: Remove some debug messages producing too much noise
  PM: Fix warning on suspend errors
  PM / Hibernate: Add newline to load_image() fail path
  PM / Hibernate: Fix error handling in save_image()
  PM / Hibernate: Fix blkdev refleaks
  PM / yenta: Split resume into early and late parts (rev. 4)