1. 07 6月, 2014 1 次提交
  2. 06 6月, 2014 4 次提交
  3. 16 5月, 2014 1 次提交
  4. 14 5月, 2014 1 次提交
  5. 25 3月, 2014 3 次提交
  6. 15 3月, 2014 1 次提交
  7. 20 2月, 2014 2 次提交
  8. 17 1月, 2014 1 次提交
  9. 15 1月, 2014 1 次提交
  10. 29 12月, 2013 2 次提交
  11. 27 12月, 2013 1 次提交
  12. 07 12月, 2013 1 次提交
    • J
      ethernet: Fix FSF address in file headers · 0ab75ae8
      Jeff Kirsher 提交于
      Several files refer to an old address for the Free Software Foundation
      in the file header comment.  Resolve by replacing the address with
      the URL <http://www.gnu.org/licenses/> so that we do not have to keep
      updating the header comments anytime the address changes.
      
      CC: Santosh Raspatur <santosh@chelsio.com>
      CC: Dimitris Michailidis <dm@chelsio.com>
      CC: Michael Chan <mchan@broadcom.com>
      CC: Santiago Leon <santil@linux.vnet.ibm.com>
      CC: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      CC: Olof Johansson <olof@lixom.net>
      CC: Manish Chopra <manish.chopra@qlogic.com>
      CC: Sony Chacko <sony.chacko@qlogic.com>
      CC: Rajesh Borundia <rajesh.borundia@qlogic.com>
      CC: Nicolas Pitre <nico@fluxnic.net>
      CC: Steve Glendinning <steve.glendinning@shawell.net>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0ab75ae8
  13. 26 11月, 2013 2 次提交
  14. 30 10月, 2013 1 次提交
    • M
      MIPS: DECstation I/O ASIC DMA interrupt classes · 0fabe102
      Maciej W. Rozycki 提交于
      This change complements commits d0da7c002f7b2a93582187a9e3f73891a01d8ee4
      [MIPS: DEC: Convert to new irq_chip functions] and
      5359b938 [MIPS: DECstation I/O ASIC DMA
      interrupt handling fix] and implements automatic handling of the two
      classes of DMA interrupts the I/O ASIC implements, informational and
      errors.
      
      Informational DMA interrupts do not stop the transfer and use the
      `handle_edge_irq' handler that clears the request right away so that
      another request may be recorded while the previous is being handled.
      
      DMA error interrupts stop the transfer and require a corrective action
      before DMA can be reenabled.  Therefore they use the `handle_fasteoi_irq'
      handler that only clears the request on the way out.  Because MIPS
      processor interrupt inputs, one of which the I/O ASIC's interrupt
      controller is cascaded to, are level-triggered it is recommended that
      error DMA interrupt action handlers are registered with the IRQF_ONESHOT
      flag set so that they are run with the interrupt line masked.
      
      This change removes the export of clear_ioasic_dma_irq that now does not
      have to be called by device drivers to clear interrupts explicitly
      anymore.  Originally these interrupts were cleared in the .end handler of
      the `irq_chip' structure, before it was removed.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5874/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      0fabe102
  15. 18 10月, 2013 2 次提交
  16. 03 10月, 2013 1 次提交
  17. 28 9月, 2013 1 次提交
  18. 24 9月, 2013 1 次提交
    • J
      amd/7990: Remove extern from function prototypes · 44da5c2f
      Joe Perches 提交于
      There are a mix of function prototypes with and without extern
      in the kernel sources.  Standardize on not using extern for
      function prototypes.
      
      Function prototypes don't need to be written with extern.
      extern is assumed by the compiler.  Its use is as unnecessary as
      using auto to declare automatic/local variables in a block.
      Signed-off-by: NJoe Perches <joe@perches.com>
      44da5c2f
  19. 21 9月, 2013 1 次提交
  20. 13 9月, 2013 2 次提交
    • M
      MIPS: DECstation I/O ASIC DMA interrupt handling fix · 5359b938
      Maciej W. Rozycki 提交于
      This change complements commit d0da7c002f7b2a93582187a9e3f73891a01d8ee4
      and brings clear_ioasic_irq back, renaming it to clear_ioasic_dma_irq at
      the same time, to make I/O ASIC DMA interrupts functional.
      
      Unlike ordinary I/O ASIC interrupts DMA interrupts need to be deasserted
      by software by writing 0 to the respective bit in I/O ASIC's System
      Interrupt Register (SIR), similarly to how CP0.Cause.IP0 and CP0.Cause.IP1
      bits are handled in the CPU (the difference is SIR DMA interrupt bits are
      R/W0C so there's no need for an RMW cycle).  Otherwise the handler is
      reentered over and over again.
      
      The only current user is the DEC LANCE Ethernet driver and its extremely
      uncommon DMA memory error handler that does not care when exactly the
      interrupt is cleared.  Anticipating the use of DMA interrupts by the Zilog
      SCC driver this change however exports clear_ioasic_dma_irq for device
      drivers to choose the right application-specific sequence to clear the
      request explicitly rather than calling it implicitly in the .irq_eoi
      handler of `struct irq_chip'.  Previously these interrupts were cleared in
      the .end handler of the said structure, before it was removed.
      Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/5826/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5359b938
    • M
      ethernet: amd: remove deprecated IRQF_DISABLED · 7bebd005
      Michael Opdenacker 提交于
      This patch proposes to remove the IRQF_DISABLED flag from
      drivers/net/ethernet/amd/sun3lance.c
      
      It's a NOOP since 2.6.35 and it will be removed one day.
      Signed-off-by: NMichael Opdenacker <michael.opdenacker@free-electrons.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7bebd005
  21. 31 8月, 2013 1 次提交
  22. 03 8月, 2013 1 次提交
  23. 15 7月, 2013 1 次提交
  24. 20 6月, 2013 2 次提交
  25. 28 5月, 2013 1 次提交
  26. 26 5月, 2013 1 次提交
  27. 23 5月, 2013 1 次提交
  28. 20 4月, 2013 2 次提交