This implements the cgs interface for allocating
GPU memory.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the interface for atombios command
and data table access.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the irq src registrar.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the pciconfig register accessors.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the MMIO register accessors.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

CGS (Common Graphics Services) is an AMD cross component
abstraction layer to designed to better encapsulate
specific IP block drivers so different teams can effectively
work on differnet IP block drivers independently. It provides
a common interface for things like accessing registers,
allocating GPU memory, and registering interrupt sources.
The plan is to eventually move more and more IP drivers to
this interface.  The first user is the ACP IP driver.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

In function 'amdgpu_uvd_cs_pass2':
warning: 'min_ctx_size' may be used uninitialized in this function
  buf_sizes[0x4] = min_ctx_size;
                 ^
note: 'min_ctx_size' was declared here
  unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
                                                          ^
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

This reverts commit 78ad5cdd.
This commit breaks dpm and suspend/resume on CZ.

Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Use the newly created wrapper drm_fb_helper functions instead of calling
core fbdev functions directly. They also simplify the fb_info creation.

v3:
- Don't touch remove_conflicting_framebuffers

v2:
- Fixed PTR_ERR issue mentioned by kbuild bot

Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "Christian König" <christian.koenig@amd.com>
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

The fw_version and feature_verion should be set correctly when the
firmwares are loaded by SMU on Tonga/Carrzio/Iceland
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Expose feature version to user space for RLC/MEC/MEC2 ucode as well

v2: fix coding style
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

gfx_v7_0_print_status contains a for loop on variable queue which does
not update this variable between each iteration.  This is bug is
reported by clang while building allmodconfig LLVMLinux on x86_64:

    drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:5126:19: error: variable
    'queue' used in loop condition not modified in loop body
    [-Werror,-Wloop-analysis]
                for (queue = 0; queue < 8; i++) {
                                ^~~~~

Fix this by incrementing variable queue instead of i in this loop.
Signed-off-by: NNicolas Iooss <nicolas.iooss_linux@m4x.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Always set num_rbs to 2 for CZ.  The 1 RB parts are often harvest
configs.  The will get sorted out in mesa when we program
PA_SC_RASTER_CONFIG[_1].
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

A logical AND operation was used during mask and shift, instead of a
bitwise AND operation. This patch fixes this bug by changing the
operation to bitwise AND.
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

The wrong define was used to check if the hqd is still active

v2: Don't use SHIFT as the MASK is already shifted
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

hdp flush is not needed for IBs that dispatched from kernel inside
because there is no video memory host access
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

compute ring didn't use const engine byfar, so ignore CE things in
compute routine
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

We recently changed the drm_amdgpu_info_device struct so now there is
a 4 byte hole at the end.  We need to initialize it so we don't disclose
secret information from the stack.

Fixes: fa92754e ('drm/amdgpu: add VCE harvesting instance query')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If we fail during device init, record what state each
block is in so that we can tear down clearly.

Fixes various problems on device init failure.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

VCE, UVD DPM work similarly to SCLK DPM.  Report the current
clock levels for UVD and VCE via debugfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

CZ uses a different set of registers compared to previous asics
and supports separate NB and GFX planes.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NLeo Liu <leo.liu@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

For boards with bad VCE blocks, only configure the working
block.

v2: use the harvest info for pipe setup
v3: fix mask check as noted by Leo
v4: add dGPU support

Reviewed-by: Christian König <christian.koenig@amd.com> (v2)
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This doesn't seem strictly necessary with Tonga right now, but that might
change with future power management enhancements.
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>

Something (ATOM BIOS?) seems to be clobbering the LB_INTERRUPT_MASK
register while the CRTC is off, which caused e.g. glxgears or
gnome-shell to hang after a modeset.
Reviewed-and-Tested-by: NAlex Deucher <alexander.deucher@amd.com>
Tested-by: NSonny Jiang <sonny.jiang@amd.com>
Signed-off-by: NMichel Dänzer <michel.daenzer@amd.com>

Signed-off-by: NBen Goz <ben.goz@amd.com>
Reviewed-by: NYair Shachar <yair.shachar@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch makes use of the new amd headers (that are part of the new
amdgpu driver), instead of private defines.
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

The MAP_QUEUES packet length for Carrizo is different than for Kaveri.
Therefore, we now need to calculate the runlist length with regard to the
underlying H/W.
Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch adds support for the VI APU in the DQM module.

Most of the functionality of DQM is shared between CI and VI. Therefore,
only a handful of functions are required to be in the
H/W-specific part of DQM.
Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch implements all the VI MQD manager functions.
This is done in a different file as the MQD format is different
between CI and VI
Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch adds the PCI IDs of supported CZ devices to the
supported_devices structure in amdkfd. That structure is used during the
amdkfd probing stage, to check if the currently probed device is eligible
to be handled by amdkfd.
Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch adds the gfx8 interface file between amdgpu and amdkfd. This
interface file is currently in use when running on a Carrizo-based
system.

The interface itself is represented by a pointer to struct
kfd_dev. The pointer is located inside amdgpu_device structure.

All the register accesses that amdkfd need are done using this
interface. This allows us to avoid direct register accesses in
amdkfd proper, while also allows us to avoid locking between
amdkfd and amdgpu.

The single exception is the doorbells that are used in both of
the drivers. However, because they are located in separate pci
bar pages, the danger of sharing registers between the drivers
is minimal.

Having said that, we are planning to move the doorbells as well
to amdgpu.
Signed-off-by: NBen Goz <ben.goz@amd.com>
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch adds the gfx7 interface file between amdgpu and amdkfd. This
interface file mirrors (some) of the functions in radeon_kfd.c
(the interface file between radeon and amdkfd).

The gfx7 interface is used when it is run on a Kaveri-based system.

This interface file was used for bring-up of amdkfd on amdgpu and for
debugging purposes. For users who would like to run HSA on Kaveri, please
use the radeon graphic driver.

Note: CONFIG_DRM_AMDGPU_CIK must be selected for amdgpu to handle Kaveri.

v2: removed MTYPE_NONCACHED enum definition as it is defined in another
patch
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>

This patch adds an interface file between amdgpu and amdkfd. This
interface file is H/W agnostic, thus containing functions that
operate the same for any AMD APU/GPU H/W generation.

The functions in this interface mirror (some) of the functions in
radeon_kfd.c (the radeon<-->amdkfd interface file). The main functions
are:

- amdgpu_amdkfd_init - initialize the amdkfd module
- amdgpu_amdkfd_load_interface - load the H/W interface according to the
  currently probed device
- amdgpu_amdkfd_device_probe - probe the device in amdkfd
- amdgpu_amdkfd_device_init - initialize the device in amdkfd
- amdgpu_amdkfd_interrupt - call the ISR of amdkfd
- amdgpu_amdkfd_suspend - suspend callback from amdgpu
- amdgpu_amdkfd_resume - resume callback from amdgpu

This patch also modifies the relevant amdgpu files, to use this new
interface.
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>