- 28 3月, 2017 1 次提交
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由 Neil Armstrong 提交于
The same Mali-450 MP3 GPU is present in the GXBB and GXL SoCs. The node is simply added in the meson-gxbb.dtsi file. For GXL, since a lot is shared with the GXM that has a Mali-T820 IP, this patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific dtsi files. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> [khilman: s/MALI/Mali in changelog] Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 24 3月, 2017 1 次提交
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由 Neil Armstrong 提交于
Since we know the GXBB and GXL/GXM share more hardware, we can safely move the remaining peripheral nodes present in the GXBB dtsi to the common GX dtsi. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 31 1月, 2017 1 次提交
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由 Martin Blumenstingl 提交于
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a 10-bit ADC while GXL and GXM provide a 12-bit ADC. Some boards use resistor ladder buttons connected through one of the ADC channels. On newer devices (GXL and GXM) some boards use pull-ups/downs to change the resistance (and thus the ADC value) on one of the ADC channels to indicate the board revision. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 19 1月, 2017 3 次提交
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由 Neil Armstrong 提交于
Add pinctrl nodes for HDMI HPD and DDC pins modes for Amlogic Meson GXL and GXBB SoCs. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Martin Blumenstingl 提交于
This adds pinctrl group nodes for the CTS and RTS pins of each serial controller. This makes it possible to enable the CTS and RTS pins which are controlled by the serial controller hardware (through the meson_uart driver). Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Martin Blumenstingl 提交于
This adds the missing node for the uart_AO_B port to the meson-gx.dtsi (as this is supported by GXBB, GXL and GXM) along with the required pinctrl pins. This is required as some boards are using it (the boards from the Khadas VIM series for example have it exposed on the pin headers). Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 18 1月, 2017 1 次提交
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由 Neil Armstrong 提交于
The current hardware is not able to run with all cores enabled at a cluster frequency superior at 1536MHz. But the currently shipped u-boot for the platform still reports an OPP table with possible DVFS frequency up to 2GHz, and will not change since the off-tree linux tree supports limiting the OPPs with a kernel parameter. A recent u-boot change reports the boot-time DVFS around 100MHz and the default performance cpufreq governor sets the maximum frequency. Previous version of u-boot reported to be already at the max OPP and left the OPP as is. Nevertheless, other governors like ondemand could setup the max frequency and make the system crash. This patch disables the DVFS clock and disables cpufreq. Fixes: 70db166a ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 11 1月, 2017 1 次提交
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由 Martin Blumenstingl 提交于
SCPI and SRAM are identical on GXBB and GXL. Moving the corresponding nodes to meson-gx adds support for the thermal sensor on GXL based devices. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Acked-by: NNeil Armstrong <narmstrong@baylibre.com> [khilman: add scpi_clocks label] Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 04 1月, 2017 1 次提交
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由 Neil Armstrong 提交于
Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards. Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 29 11月, 2016 1 次提交
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由 Kevin Hilman 提交于
The SCPI driver has an updated compatible to indicate the pre-released (pre v1.0) status of the driver. Since Amlogic used a pre-1.0 version, add that compatible as well. Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 17 11月, 2016 1 次提交
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由 Martin Blumenstingl 提交于
When the USB PHY driver was introduced the reset framework did not have support for triggering a reset pulse for shared resets. On GXBB however there is only one reset line for both PHYs (meaning we have a shared reset line). With the latest changes to the reset framework and the corresponding updates to the phy-meson8b-usb2 driver we can now pass the reset to the second PHY as well. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 16 11月, 2016 2 次提交
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由 Neil Armstrong 提交于
Move common nodes between GXBB and GXL in to the common GX dtsi. Leave the clock attributes in the GXBB dtsi for now. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 21 10月, 2016 2 次提交
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Kevin Hilman 提交于
Add binding and basic support for the SD/eMMC controller on Amlogic S905/GXBB devices. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> [narmstrong: added nodes for GX, enabled SDIO on P20x] Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 19 10月, 2016 1 次提交
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由 Neil Armstrong 提交于
For boards only supporting 10/100 ethernet over a RMII PHY link, add a separate pinctrl node. By the way, rename the existing node to rgmii specific naming in all boards dts. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 18 10月, 2016 1 次提交
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由 Neil Armstrong 提交于
Move all non-gxbb specific nodes to a common GX dtsi. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 15 9月, 2016 10 次提交
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由 Marc Zyngier 提交于
The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: NDuc Dang <dhdang@apm.com> Acked-by: NCarlo Caione <carlo@endlessm.com> Acked-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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由 Martin Blumenstingl 提交于
Add the nodes for the dwc2 USB controller and the related USB PHYs. Currently we force usb0 to host mode because OTG is currently not working in our PHY driver. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Jerome Brunet 提交于
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
This is used to configure the pins of the sd_emmc_a controller to which an SDIO module is connected (when available). Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Jerome Brunet 提交于
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Martin Blumenstingl 提交于
The Amlogic reference driver uses the "mc_val" devicetree property to configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic values for this configuration. According to the datasheet the PRG_ETHERNET_ADDR0 register is at address 0xc8834108. However, the reference driver uses 0xc8834540 instead. According to my tests, the value from the reference driver is correct. No changes are required to the board dts files because the only required configuration option is the phy-mode, which had to be configured correctly before as well. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Tested-by: NJérôme Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 02 9月, 2016 6 次提交
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由 Carlo Caione 提交于
Add the NVMEM device node in the DTSI. Signed-off-by: NCarlo Caione <carlo@endlessm.com> [khilman: dropped driver cleanup hunk] Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Carlo Caione 提交于
Add the secure monitor node in the Amlogic Meson GXBB DTSI file to enable it. Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Kevin Hilman 提交于
Add DT nodes for PWMs in EE and AO domains. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
This adds the Infrared Remote Controller node so boards with an IR remote can simply enable it. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Kevin Hilman 提交于
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Add the AO clock controller node for the AmLogic GXBB SoC. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 18 8月, 2016 1 次提交
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由 Kevin Hilman 提交于
With the clock driver upstream, switch to the real clock. Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 16 8月, 2016 1 次提交
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 07 7月, 2016 1 次提交
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由 Arnd Bergmann 提交于
This reverts commit f3abd629, which caused a build regression: arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi:48:41: fatal error: dt-bindings/clock/gxbb-clkc.h: No such file or directory We should apply this patch one merge window later, once the clk branch is merged as well. Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 24 6月, 2016 2 次提交
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由 Kevin Hilman 提交于
With the clock driver upstream, switch to the real clock. Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Michael Turquette 提交于
Add the clock controller node for the AmLogic GXBB machine. Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 15 6月, 2016 1 次提交
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 02 6月, 2016 1 次提交
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由 Neil Armstrong 提交于
Update DTSI file to add the reset controller node. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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