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  1. 07 4月, 2009 2 次提交
  3. 03 4月, 2009 1 次提交
  5. 29 3月, 2009 2 次提交
  7. 28 3月, 2009 1 次提交
  9. 21 3月, 2009 1 次提交
  11. 21 2月, 2009 1 次提交
    • M
      8250: fix boot hang with serial console when using with Serial Over Lan port · b6adea33
      由 Mauro Carvalho Chehab 提交于 
      Intel 8257x Ethernet boards have a feature called Serial Over Lan.

This feature works by emulating a serial port, and it is detected by
kernel as a normal 8250 port.  However, this emulation is not perfect, as
also noticed on changeset 7500b1f6.

Before this patch, the kernel were trying to check if the serial TX is
capable of work using IRQ's.

This were done with a code similar this:

        serial_outp(up, UART_IER, UART_IER_THRI);
        lsr = serial_in(up, UART_LSR);
        iir = serial_in(up, UART_IIR);
        serial_outp(up, UART_IER, 0);

        if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
		up->bugs |= UART_BUG_TXEN;

This works fine for other 8250 ports, but, on 8250-emulated SoL port, the
chip is a little lazy to down UART_IIR_NO_INT at UART_IIR register.

Due to that, UART_BUG_TXEN is sometimes enabled.  However, as TX IRQ keeps
working, and the TX polling is now enabled, the driver miss-interprets the
IRQ received later, hanging up the machine until a key is pressed at the
serial console.

This is the 6 version of this patch.  Previous versions were trying to
introduce a large enough delay between serial_outp and serial_in(up,
UART_IIR), but not taking forever.  However, the needed delay couldn't be
safely determined.

At the experimental tests, a delay of 1us solves most of the cases, but
still hangs sometimes.  Increasing the delay to 5us was better, but still
doesn't solve.  A very high delay of 50 ms seemed to work every time.

However, poking around with delays and pray for it to be enough doesn't
seem to be a good approach, even for a quirk.

So, instead of playing with random large arbitrary delays, let's just
disable UART_BUG_TXEN for all SoL ports.

[akpm@linux-foundation.org: fix warnings]
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: <stable@kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b6adea33
  13. 19 2月, 2009 1 次提交
  15. 18 2月, 2009 1 次提交
  17. 30 1月, 2009 2 次提交
  19. 29 1月, 2009 1 次提交
  21. 28 1月, 2009 1 次提交
  23. 26 1月, 2009 1 次提交
  25. 23 1月, 2009 1 次提交
  27. 22 1月, 2009 1 次提交
  29. 15 1月, 2009 1 次提交
  31. 07 1月, 2009 1 次提交
    • S
      Resurrect IT8172 IDE controller driver · 391ad190
      由 Shane McDonald 提交于 
      Support for the IT8172 IDE controller was removed from the kernel
sometime after 2.6.18.  Support for the only boards that used the IT8172
was removed from the kernel after 2.6.18, as they had never compiled
since 2.6.0.  However, there are a couple of platforms that use this
chip: the PMC-Sierra Xiao Hu thin-client computer, which is no longer
in production, and the Linksys NSS4000 Network Attached Storage box,
which is based on the Xiao Hu board.  I am attempting to add support
for the Xiao Hu to the kernel, and this IT8172 IDE controller is the
first bit of code in this effort.

This patch resurrects the IT8172 IDE controller code.  I began with
the 2.6.18 version of the it8172.c file, and have moved it forward so
that it works with the latest version of the kernel.  I have run this
driver on a PMC-Sierra Xiao Hu board with the 2.6.28 kernel, and
I have had no problems with it in my configuration.  The attached patch
applies cleanly against 2.6.28.
Signed-off-by: NShane McDonald <mcdonald.shane@gmail.com>
Acked-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: alan@lxorguk.ukuu.org.uk
[bart: s/HWIF(drive)/drive->hwif/]
Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      391ad190
  33. 03 1月, 2009 2 次提交
  35. 24 10月, 2008 1 次提交
  37. 22 10月, 2008 1 次提交
  39. 21 10月, 2008 1 次提交
  41. 17 10月, 2008 1 次提交
  43. 01 10月, 2008 1 次提交
  45. 25 9月, 2008 1 次提交
  47. 18 9月, 2008 2 次提交
  49. 06 9月, 2008 1 次提交
  51. 04 9月, 2008 3 次提交
  53. 16 8月, 2008 1 次提交
  55. 08 8月, 2008 1 次提交
  57. 27 7月, 2008 1 次提交
  59. 26 7月, 2008 2 次提交
    • R
      x86: add PCI IDs for AMD Barcelona PCI devices · 021f8b75
      由 Robert Richter 提交于 
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
Cc: oprofile-list <oprofile-list@lists.sourceforge.net>
Cc: Barry Kasindorf <barry.kasindorf@amd.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>
      021f8b75
    • A
      edac: i5100 new intel chipset driver · 8f421c59
      由 Arthur Jones 提交于 
      Preliminary support for the Intel 5100 MCH.  CE and UE errors are reported
along with the current DIMM label information and other memory parameters.

Reasons why this is preliminary:

1) This chip has 2 independent memory controllers which, for best
   perforance, use interleaved accesses to the DDR2 memory.  This
   architecture does not map very well to the current edac data structures
   which depend on symmetric channel access to the interleaved data.
   Without core changes, the best I could do for now is to map both memory
   controllers to different csrows (first all ranks of controller 0, then
   all ranks of controller 1).  Someone much more familiar with the edac
   core than I will probably need to come up with a more general data
   structure to handle the interleaving and de-interleaving of the two
   memory controllers.

2) I have not yet tackled the de-interleaving of the rank/controller
   address space into the physical address space of the CPU.  There is
   nothing fundamentally missing, it is just ending up to be a lot of
   code, and I'd rather keep it separate for now, esp since it doesn't
   work yet...

3) The code depends on a particular i5100 chip select to DIMM mainboard
   chip select mapping.  This mapping seems obvious to me in order to
   support dual and single ranked memory, but it is not unique and DIMM
   labels could be wrong on other mainboards.  There is no way to query
   this mapping that I know of.

4) The code requires that the i5100 is in 32GB mode.  Only 4 ranks per
   controller, 2 ranks per DIMM are supported.  I do not have hardware
   (nor do I expect to have hardware anytime soon) for the 48GB (6 ranks
   per controller) mode.

5) The serial presence detect code should be broken out into a "real"
   i2c driver so that decode-dimms.pl can work.
Signed-off-by: NArthur Jones <ajones@riverbed.com>
Signed-off-by: NDoug Thompson <dougthompson@xmission.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      8f421c59
  61. 25 7月, 2008 1 次提交
  63. 23 7月, 2008 1 次提交