1. 24 7月, 2012 1 次提交
    • D
      i2c-i801: Enable IRQ for SMBus transactions · 636752bc
      Daniel Kurtz 提交于
      Add a new 'feature' to i2c-i801 to enable using PCI interrupts.
      When the feature is enabled, then an isr is installed for the device's
      PCI IRQ.
      
      An I2C/SMBus transaction is always terminated by one of the following
      interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR.
      
      When the isr fires for one of these cases, it sets the ->status variable
      and wakes up the waitq.  The waitq then saves off the status code, and
      clears ->status (in preparation for some future transaction).
      The SMBus controller generates an INTR irq at the end of each
      transaction where INTREN was set in the HST_CNT register.
      
      No locking is needed around accesses to priv->status since all writes to
      it are serialized: it is only ever set once in the isr at the end of a
      transaction, and cleared while no interrupts can occur.  In addition, the
      I2C adapter lock guarantees that entire I2C transactions for a single
      adapter are always serialized.
      
      For this patch, the INTREN bit is set only for SMBus block, byte and word
      transactions, but not for I2C reads or writes.  The use of the DS
      (BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in
      a subsequent patch.
      
      The interrupt feature has only been enabled for COUGARPOINT hardware.
      In addition, it is disabled if SMBus is using the SMI# interrupt.
      Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      636752bc
  2. 27 3月, 2012 1 次提交
  3. 25 5月, 2011 1 次提交
  4. 20 3月, 2011 1 次提交
  5. 01 11月, 2010 2 次提交
  6. 22 5月, 2010 1 次提交
  7. 02 3月, 2010 1 次提交
  8. 23 10月, 2008 1 次提交
  9. 25 2月, 2008 1 次提交
  10. 28 1月, 2008 1 次提交
    • J
      i2c-i801: Implement I2C block read support · 6342064c
      Jean Delvare 提交于
      I2C block read is supported since the ICH5. I couldn't get it to work
      using the block buffer, so it's using the old-style byte-by-byte mode
      for now.
      
      Note: I'm also updating the driver author... The i2c-i801 driver was
      really written by Mark Studebaker, even though he based his work on
      the i2c-piix4 driver which was written by Philip Edelbrock.
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      6342064c
  11. 14 10月, 2007 1 次提交
  12. 12 7月, 2007 1 次提交
    • O
      i2c-i801: Use the internal 32-byte buffer on ICH4+ · 7edcb9ab
      Oleg Ryjkov 提交于
      Add an ability to utilize the internal SRAM buffer on ICH4
      and newer host controllers to speed up execution of block operations.
      
      I've split the code so that it is more clear which block transaction is
      performed.
      
      First of all the host controller's type is identified. isich4 is set when
      we think that the controller has the internal buffer. Then, before every
      block transaction, if isich4 is set, we attempt to enable the E32B bit in
      SMBAUXCTL register.
      Signed-off-by: NOleg Ryjkov <olegr@google.com>
      Signed-off-by: NJean Delvare <khali@linux-fr.org>
      7edcb9ab
  13. 14 2月, 2007 1 次提交
  14. 11 12月, 2006 1 次提交
  15. 23 6月, 2006 1 次提交
  16. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4