- 24 7月, 2012 1 次提交
-
-
由 Daniel Kurtz 提交于
Add a new 'feature' to i2c-i801 to enable using PCI interrupts. When the feature is enabled, then an isr is installed for the device's PCI IRQ. An I2C/SMBus transaction is always terminated by one of the following interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR. When the isr fires for one of these cases, it sets the ->status variable and wakes up the waitq. The waitq then saves off the status code, and clears ->status (in preparation for some future transaction). The SMBus controller generates an INTR irq at the end of each transaction where INTREN was set in the HST_CNT register. No locking is needed around accesses to priv->status since all writes to it are serialized: it is only ever set once in the isr at the end of a transaction, and cleared while no interrupts can occur. In addition, the I2C adapter lock guarantees that entire I2C transactions for a single adapter are always serialized. For this patch, the INTREN bit is set only for SMBus block, byte and word transactions, but not for I2C reads or writes. The use of the DS (BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in a subsequent patch. The interrupt feature has only been enabled for COUGARPOINT hardware. In addition, it is disabled if SMBus is using the SMI# interrupt. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 27 3月, 2012 1 次提交
-
-
由 Seth Heasley 提交于
Add the SMBus controller device IDs for the Intel Lynx Point PCH. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 25 5月, 2011 1 次提交
-
-
由 Seth Heasley 提交于
This patch adds the SMBus controller DeviceID for the Intel Panther Point PCH. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 20 3月, 2011 1 次提交
-
-
由 Seth Heasley 提交于
Add the SMBus Controller DeviceIDs for the Intel DH89xxCC PCH. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 01 11月, 2010 2 次提交
-
-
由 David Woodhouse 提交于
These are the extra 'Integrated Device Function' SMBus controllers found on the Patsburg chipset. Mention the absence of slave mode support. Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
由 Seth Heasley 提交于
Add support for the Intel Patsburg PCH SMBus Controller. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 22 5月, 2010 1 次提交
-
-
由 Jean Delvare 提交于
Let the user disable selected features normally supported by the device. This makes it possible to work around possible driver or hardware bugs if the feature in question doesn't work as intended for whatever reason. Signed-off-by: NJean Delvare <khali@linux-fr.org> Cc: Felix Rubinstein <felixru@gmail.com>
-
- 02 3月, 2010 1 次提交
-
-
由 Seth Heasley 提交于
Add the Intel Cougar Point (PCH) SMBus controller device IDs. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 23 10月, 2008 1 次提交
-
-
由 Seth Heasley 提交于
Adds the Intel Ibex Peak (PCH) SMBus Controller Device IDs. Signed-off-by: NSeth Heasley <seth.heasley@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 25 2月, 2008 1 次提交
-
-
由 Gaston, Jason D 提交于
Add the Intel ICH10 SMBus Controller DeviceID's and updates Tolapai support. Signed-off-by: NJason Gaston <jason.d.gaston@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 28 1月, 2008 1 次提交
-
-
由 Jean Delvare 提交于
I2C block read is supported since the ICH5. I couldn't get it to work using the block buffer, so it's using the old-style byte-by-byte mode for now. Note: I'm also updating the driver author... The i2c-i801 driver was really written by Mark Studebaker, even though he based his work on the i2c-piix4 driver which was written by Philip Edelbrock. Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 14 10月, 2007 1 次提交
-
-
由 Jason Gaston 提交于
Add the Intel Tolapai SMBus Controller DID. Signed-off-by: NJason Gaston <jason.d.gaston@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 12 7月, 2007 1 次提交
-
-
由 Oleg Ryjkov 提交于
Add an ability to utilize the internal SRAM buffer on ICH4 and newer host controllers to speed up execution of block operations. I've split the code so that it is more clear which block transaction is performed. First of all the host controller's type is identified. isich4 is set when we think that the controller has the internal buffer. Then, before every block transaction, if isich4 is set, we attempt to enable the E32B bit in SMBAUXCTL register. Signed-off-by: NOleg Ryjkov <olegr@google.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 14 2月, 2007 1 次提交
-
-
由 Jean Delvare 提交于
This is a frequently asked question so it deserves a paragraph in the driver documentation. Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 11 12月, 2006 1 次提交
-
-
由 Jason Gaston 提交于
Add the Intel ICH9/ICH8/ESB2 SMBus Controller text to i2c-i801 documentation. Signed-off-by: NJason Gaston <jason.d.gaston@intel.com> Signed-off-by: NJean Delvare <khali@linux-fr.org>
-
- 23 6月, 2006 1 次提交
-
-
由 Jean Delvare 提交于
i2c-i801: Remove force_addr parameter Remove the force_addr module parameter. It doesn't appear to ever have been needed, and PCI resources shouldn't be arbitrarily changed anyway. Signed-off-by: NJean Delvare <khali@linux-fr.org> Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
-
- 17 4月, 2005 1 次提交
-
-
由 Linus Torvalds 提交于
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
-