1. 09 10月, 2012 13 次提交
  2. 06 10月, 2012 4 次提交
    • D
      Revert strace hiccups fix. · 2863bc54
      David S. Miller 提交于
      This reverts commit 40138249 and
      ffa9009c.
      
      There are problems with how the flag bytes were rearranged, in
      particular we really can't move values down into the lowest
      16 bits since those are used for individual state bits.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2863bc54
    • D
      sparc64: Niagara-4 bzero/memset, plus use MRU stores in page copy. · 9f825962
      David S. Miller 提交于
      This adds optimized memset/bzero/page-clear routines for Niagara-4.
      
      We basically can do what powerpc has been able to do for a decade (via
      the "dcbz" instruction), which is use cache line clearing stores for
      bzero and memsets with a 'c' argument of zero.
      
      As long as we make the cache initializing store to each 32-byte
      subblock of the L2 cache line, it works.
      
      As with other Niagara-4 optimized routines, the key is to make sure to
      avoid any usage of the %asi register, as reads and writes to it cost
      at least 50 cycles.
      
      For the user clear cases, we don't use these new routines, we use the
      Niagara-1 variants instead.  Those have to use %asi in an unavoidable
      way.
      
      A Niagara-4 8K page clear costs just under 600 cycles.
      
      Add definitions of the MRU variants of the cache initializing store
      ASIs.  By default, cache initializing stores install the line as Least
      Recently Used.  If we know we're going to use the data immediately
      (which is true for page copies and clears) we can use the Most
      Recently Used variant, to decrease the likelyhood of the lines being
      evicted before they get used.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9f825962
    • D
      compat: move compat_siginfo_t definition to asm/compat.h · 751f409d
      Denys Vlasenko 提交于
      This is a preparatory patch for the introduction of NT_SIGINFO elf note.
      
      Make the location of compat_siginfo_t uniform across eight architectures
      which have it.  Now it can be pulled in by including asm/compat.h or
      linux/compat.h.
      
      Most of the copies are verbatim.  compat_uid[32]_t had to be replaced by
      __compat_uid[32]_t.  compat_uptr_t had to be moved up before
      compat_siginfo_t in asm/compat.h on a several architectures (tile already
      had it moved up).  compat_sigval_t had to be relocated from linux/compat.h
      to asm/compat.h.
      Signed-off-by: NDenys Vlasenko <vda.linux@googlemail.com>
      Cc: Oleg Nesterov <oleg@redhat.com>
      Cc: Amerigo Wang <amwang@redhat.com>
      Cc: "Jonathan M. Foote" <jmfoote@cert.org>
      Cc: Roland McGrath <roland@hack.frob.com>
      Cc: Pedro Alves <palves@redhat.com>
      Cc: Fengguang Wu <fengguang.wu@intel.com>
      Cc: Stephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      751f409d
    • J
      cross-arch: don't corrupt personality flags upon exec() · 16f3e95b
      Jiri Kosina 提交于
      Historically, the top three bytes of personality have been used for
      things such as ADDR_NO_RANDOMIZE, which made sense only for specific
      architectures.
      
      We now however have a flag there that is general no matter the
      architecture (UNAME26); generally we have to be careful to preserve the
      personality flags across exec().
      
      This patch tries to fix all architectures that forcefully overwrite
      personality flags during exec() (ppc32 and s390 have been fixed recently
      by commits f9783ec8 ("[S390] Do not clobber personality flags on
      exec") and 59e4c3a2 ("powerpc/32: Don't clobber personality flags on
      exec") in a similar way already).
      Signed-off-by: NJiri Kosina <jkosina@suse.cz>
      Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
      Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Mark Salter <msalter@redhat.com>
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: Jesper Nilsson <jesper.nilsson@axis.com>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
      Cc: Richard Kuo <rkuo@codeaurora.org>
      Cc: Hirokazu Takata <takata@linux-m32r.org>
      Cc: Geert Uytterhoeven <geert@linux-m68k.org>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com>
      Cc: Jonas Bonn <jonas@southpole.se>
      Cc: Chen Liqin <liqin.chen@sunplusct.com>
      Cc: Lennox Wu <lennox.wu@gmail.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Chris Zankel <chris@zankel.net>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      16f3e95b
  3. 05 10月, 2012 2 次提交
  4. 04 10月, 2012 1 次提交
  5. 03 10月, 2012 3 次提交
  6. 29 9月, 2012 1 次提交
  7. 28 9月, 2012 2 次提交
  8. 27 9月, 2012 2 次提交
  9. 22 9月, 2012 4 次提交
  10. 19 9月, 2012 2 次提交
  11. 18 9月, 2012 1 次提交
  12. 16 9月, 2012 3 次提交
  13. 07 9月, 2012 2 次提交
    • D
      sparc64: Use cpu_pgsz_mask for linear kernel mapping config. · c69ad0a3
      David S. Miller 提交于
      This required a little bit of reordering of how we set up the memory
      management early on.
      
      We now only know the final values of kern_linear_pte_xor[] after we
      take over the trap table and start processing TLB misses ourselves.
      
      So once we fill those values in we re-clear the kernel's 4M TSB and
      flush the TLBs.  That way if we find we support larger than 4M pages
      we won't have any stale smaller page size entries in the TSB.
      
      SUN4U Panther support for larger page sizes should now be extremely
      trivial but I have no hardware on which to test it and I believe
      that some of the sun4u TLB miss assembler needs to be audited first
      to make sure it really can handle larger than 4M PTEs properly.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c69ad0a3
    • D
      sparc64: Probe cpu page size support more portably. · ce33fdc5
      David S. Miller 提交于
      On sun4v, interrogate the machine description.  This code is extremely
      defensive in nature, and a lot of the checks can probably be removed.
      
      On sun4u things are a lot simpler.  There are the page sizes all chips
      support, and then Panther adds 32MB and 256MB pages.
      
      Report the probed value in /proc/cpuinfo
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ce33fdc5