On few platforms, for power efficiency, we want the device to be
configured for a specific OPP while we put the device in suspend state.

Add an optional property in operating-points-v2 bindings for that.
Suggested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NNishanth Menon <nm@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

On some platforms (Like Qualcomm's SoCs), it is not decided until
runtime on what OPPs to use. The OPP tables can be fixed at compile
time, but which table to use is found out only after reading some efuses
(sort of an prom) and knowing characteristics of the SoC.

To support such platform we need to pass multiple OPP tables per device
and hardware should be able to choose one and only one table out of
those.

Update operating-points-v2 bindings to support that.
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Current OPP (Operating performance point) device tree bindings have been
insufficient due to the inflexible nature of the original bindings. Over
time, we have realized that Operating Performance Point definitions and
usage is varied depending on the SoC and a "single size (just frequency,
voltage) fits all" model which the original bindings attempted and
failed.

The proposed next generation of the bindings addresses by providing a
expandable binding for OPPs and introduces the following common
shortcomings seen with the original bindings:

- Getting clock/voltage/current rails sharing information between CPUs.
  Shared by all cores vs independent clock per core vs shared clock per
  cluster.

- Support for specifying current levels along with voltages.

- Support for multiple regulators.

- Support for turbo modes.

- Other per OPP settings: transition latencies, disabled status, etc.?

- Expandability of OPPs in future.

This patch introduces new bindings "operating-points-v2" to get these problems
solved. Refer to the bindings for more details.

We now have multiple versions of OPP binding and only one of them should
be used per device.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Add device tree bindings for the DA9063 OnKey driver.
Signed-off-by: NSteve Twiss <stwiss.opensource@diasemi.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NRichard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Fix typo in 'Multifunction'.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch adds device tree binding documentation for
the flash cell of the Maxim max77693 multifunctional device.
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

We are about to add a new driver to support new features like using the
TDMA engine to offload the CPU.
Orion, Dove and Kirkwood platforms are already using the mv_cesa driver,
but Orion SoCs do not embed the TDMA engine, which means we will have to
differentiate them if we want to get TDMA support on Dove and Kirkwood.
In the other hand, the migration from the old driver to the new one is not
something all people are willing to do without first auditing the new
driver.
Hence we have to support the new compatible in the mv_cesa driver so that
new platforms with updated DTs can still attach their crypto engine device
to this driver.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The mv_cesa driver currently expects the SRAM memory region to be passed
as a platform device resource.

This approach implies two drawbacks:
- the DT representation is wrong
- the only one that can access the SRAM is the crypto engine

The last point is particularly annoying in some cases: for example on
armada 370, a small region of the crypto SRAM is used to implement the
cpuidle, which means you would not be able to enable both cpuidle and the
CESA driver.

To address that problem, we explicitly define the SRAM device in the DT
and then reference the sram node from the crypto engine node.

Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Add sama5d2 support to irq-atmel-aic5.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Cc: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: <linux-arm-kernel@lists.infradead.org>
Link: http://lkml.kernel.org/r/1434632855-27272-1-git-send-email-nicolas.ferre@atmel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

- add new property "atmel,fifo-size"
- change "cs-gpios" to optional for SPI controller version >= 2.

Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the SPI controller
can be integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older SPI controllers don't
embed FIFO at all.

Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unused spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.

Finally, on a given SoC, there can be several instances of the SPI
controller with different FIFO sizes. This explain why we'd rather use a
dedicated DT property than use the "compatible" property.

For instance, sama5d2x SoCs come with some SPI controllers, the ones
inside Flexcoms, integrating 32 data FIFOs whereas other SPI controllers
use 16 data FIFOs. All these SPI controllers share the same IP version.
Signed-off-by: NCyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Add an SPMI regulator driver for Qualcomm's PM8841, PM8941, and
PM8916 PMICs. This driver is based largely on code from
codeaurora.org[1].

[1] https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/regulator/qpnp-regulator.c?h=msm-3.10
Cc: David Collins <collinsd@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Document the device-tree binding of Mediatek MMC host
Signed-off-by: NChaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

DSPI driver has been updated and support more compatible strings.
This patch update the DT binding documentation.
Signed-off-by: NHaikun Wang <haikun.wang@freescale.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some ECs need a little time for waking up before they can accept
SPI data at a high speed. Add a "google,cros-ec-spi-pre-delay"
property to the DT binding to configure this.

If this property isn't set, then no delay will be added. However,
if set it will cause a delay equal to the value passed to it to
be inserted at the beginning of a transaction.
Signed-off-by: NAlexandru M Stan <amstan@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NLee Jones <lee.jones@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add bindings documentation for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: NRanjit Waghmode <ranjit.waghmode@xilinx.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some regulators can limit their input current (typically annotated
as ilim). Add an op (set_input_current_limit) and a DT property +
constraint to support this.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some regulators support a "soft start" feature where the voltage
ramps up slowly when the regulator is enabled. Add an op
(set_soft_start) and a DT property + constraint to support this.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some regulators need to be configured to pull down a resistor
when the regulator is disabled. Add an op (set_pull_down) and a
DT property + constraint to support this.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

Some regulators have a fixed load that isn't captured by
consumers that the kernel knows about. Add a constraint to
support this.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMark Brown <broonie@kernel.org>

The commit edd4ab05 ("power: max17042_battery: add HEALTH and TEMP_*
properties support") added support for setting voltage and temperature
thresholds with platform data. For DeviceTree default of 0 was always
used.

This caused reporting battery health always as over voltage or
over heated.
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Fixes: edd4ab05 ("power: max17042_battery: add HEALTH and TEMP_* properties support")
Signed-off-by: NSebastian Reichel <sre@kernel.org>

Added support to Zynq Ultrascale+ MPSoC on the existing zynq
gpio driver.
Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a GPIO driver for the General I/O block on Axis ETRAX FS SoCs.
Signed-off-by: NRabin Vincent <rabin@rab.in>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Maxim MAX77621 device is high-efficiency, three-phase,
DC-DC step-down switching regulator delivers peak
output currents up to 16A. This device is extension of
MAX8973 and compatible with the register definition.

The MAX77621 has the SHUTDOWN pin which is EN pin on the
MAX8973. On MAX77621, the SHUTDOWN pin (active low) reset
device register to its POR/OTP value. The voltage output
is enabled when SHUTDONW pin is HIGH and EN bit on VOUT
register is HIGH.

For MAX8973, VOUT is enabled when EN bit or EN pin is high.

Add support of the MAX77621 device on max8973 regulator driver
with following changes:
- Make sure SHUTDOWN pin is set HIGH through GPIO calls if
  GPIO from AP connected to SHUTDOWN pin provided.
- Enable/disable the rail through register access only.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NMark Brown <broonie@kernel.org>

APM X-Gene v1 SoC supports its own implementation of MSI, which is not
compliant to GIC V2M specification for MSI Termination.

There is a single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
This MSI block supports 2048 MSI termination ports coalesced into 16
physical HW IRQ lines and shared across all 5 PCIe ports.

As there are only 16 HW IRQs to serve 2048 MSI vectors, to support
set_affinity correctly for each MSI vectors, the 16 HW IRQs are statically
allocated to 8 X-Gene v1 cores (2 HW IRQs for each cores).  To steer MSI
interrupt to target CPU, MSI vector is moved around these HW IRQs lines.
With this approach, the total MSI vectors this driver supports is reduced
to 256.

[bhelgaas: squash doc, driver, maintainer update]
Signed-off-by: NDuc Dang <dhdang@apm.com>
Signed-off-by: NTanmay Inamdar <tinamdar@apm.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>

Add missing documentation for required properties:
  - interrupt-controller,
  - parent interrupts (one entry per provided interrupt).

Add missing documentation for optional properties:
  - functional clock (managed since commit 705bc96c ("irqchip:
    renesas-intc-irqpin: Add minimal runtime PM support")),
  - power-domains.

Add an example, taken from r8a7740.dtsi.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1432891663-23641-1-git-send-email-geert%2Brenesas@glider.beSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This adds documentation of device tree bindings for the
STM32 timer.
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This adds documentation of device tree bindings for the
ARM System timer.
Tested-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Add DT bindings documentation for lpc3220-timer. This timer is
used as clocksource on many NXP platforms.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Using specific compatible string in binding doc to make the binding
more clear.
It's also used to avoid checkpatch warning in the future like follows:
WARNING: DT compatible string "fsl,imx6sx-usdhc" appears un-documented --
check ./Documentation/devicetree/bindings/
+       { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },

total: 0 errors, 1 warnings, 18 lines checked
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

MMCIF IP on R-Car series has parent clock which can be set several rate,
and it was not implemented on old SH-Mobile series (= SH-Mobile series
parent clock was fixed rate) R-Car series MMCIF can use more high speed
access if it setups parent clock. This patch adds parent clock setup
method. It will be used if DT has "max-frequency", and then, this driver
assumes it is booted on R-Car Gen2 or later SoC. Because SH-Mobile series
(which doesn't boot from DT) and R-Car series (which boots from DT) have
different divider.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
[Ulf: Silence compiler warning]

Add bindings for hi6220 mmc support
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

Allow to specify in the device-tree that no physical write-protect signal
is connected to a particular instance of a MMC controller. Setting the
property will cause the core will assume that the SD card is always
read-write.

The name for the new property is 'disable-wp' and was chosen based on the
property with the same function from the Synopsys designware mobile storage
host controller DT bindings specification.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan4.9a version of controller.
Signed-off-by: NSuman Tripathi <stripathi@apm.com>
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>

This patch adds support for the ntc thermistor NCPXXWF104 series.

Cc: Jean Delvare <jdelvare@suse.de>
Cc: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: NBeomho Seo <beomho.seo@samsung.com>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Signed-off-by: NAnda-Maria Nicolae <anda-maria.nicolae@intel.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
[added default values to optional properties]
Signed-off-by: NSebastian Reichel <sre@kernel.org>

Signed-off-by: NAnda-Maria Nicolae <anda-maria.nicolae@intel.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: NSebastian Reichel <sre@kernel.org>