1. 19 7月, 2011 1 次提交
    • D
      ARM: 6999/1: head, zImage: Always Enter the kernel in ARM state · 540b5738
      Dave Martin 提交于
      Currently, the documented kernel entry requirements are not
      explicit about whether the kernel should be entered in ARM or
      Thumb, leading to an ambiguitity about how to enter Thumb-2
      kernels.  As a result, the kernel is reliant on the zImage
      decompressor to enter the kernel proper in the correct instruction
      set state.
      
      This patch changes the boot entry protocol for head.S and Image to
      be the same as for zImage: in all cases, the kernel is now entered
      in ARM.
      
      Documentation/arm/Booting is updated to reflect this new policy.
      
      A different rule will be needed for Cortex-M class CPUs as and when
      support for those lands in mainline, since these CPUs don't support
      the ARM instruction set at all: a note is added to the effect that
      the kernel must be entered in Thumb on such systems.
      Signed-off-by: NDave Martin <dave.martin@linaro.org>
      Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      540b5738
  2. 16 2月, 2011 1 次提交
  3. 08 10月, 2010 1 次提交
  4. 24 11月, 2009 1 次提交
  5. 24 7月, 2009 2 次提交
  6. 01 9月, 2008 1 次提交
  7. 07 8月, 2008 1 次提交
  8. 08 5月, 2007 1 次提交
  9. 30 11月, 2006 1 次提交
  10. 29 9月, 2006 1 次提交
    • H
      [ARM] nommu: confirms the CR_V bit in nommu mode · 6afd6fae
      Hyok S. Choi 提交于
      In nommu mode, the exception vector location depends on the platforms.
      Some of the implementations may have some special exception control
      forwarding method in their ROM/flash and for some of them has its own
      re-mapping mechanism by the h/w.
      
      This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
      turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
      This feature depends on CP15 and does not supported by ARM740.
      Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6afd6fae
  11. 28 9月, 2006 1 次提交
    • H
      [ARM] nommu: manage the CP15 things · f12d0d7c
      Hyok S. Choi 提交于
      All the current CP15 access codes in ARM arch can be categorized and
      conditioned by the defines as follows:
      
           Related operation	Safe condition
        a. any CP15 access	!CPU_CP15
        b. alignment trap	CPU_CP15_MMU
        c. D-cache(C-bit)	CPU_CP15
        d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
      				CPU_ARM720 || CPU_ARM740 ||
      				CPU_XSCALE || CPU_XSC3 )
        e. alternate vector	CPU_CP15 && !CPU_ARM740
        f. TTB		CPU_CP15_MMU
        g. Domain		CPU_CP15_MMU
        h. FSR/FAR		CPU_CP15_MMU
      
      For example, alternate vector is supported if and only if
      "CPU_CP15 && !CPU_ARM740" is satisfied.
      Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      f12d0d7c
  12. 01 7月, 2006 1 次提交
  13. 25 6月, 2006 1 次提交
  14. 05 5月, 2006 1 次提交
  15. 24 4月, 2006 1 次提交
  16. 27 3月, 2006 1 次提交