- 04 1月, 2017 1 次提交
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由 Rodrigo Vivi 提交于
No functional changes. Apparently spec has been changed the valid table showing 0x192A as Server GT4 while 0x193A is Server GT4e. Libdrm and Mesa already have this right. So let's fix the ref here. Cc: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: NBen Widawsky <benjamin.widawsky@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1483471672-10450-1-git-send-email-rodrigo.vivi@intel.com
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- 03 1月, 2017 3 次提交
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After commit 1c74eeaf ("drm/i915: Move number of scalers initialization to runtime init"), scalers are not initialized properly for skl and glk since num_scalers is left as 0 for those platforms. Fixes: 1c74eeaf ("drm/i915: Move number of scalers initialization to runtime init") Cc: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> (v2) Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Tested-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1483365281-10569-1-git-send-email-ander.conselvan.de.oliveira@intel.com
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由 Chris Wilson 提交于
Ville explained that the wakelock was being acquired during set-idle in order to flush the voltage change from the punit. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170102152845.32352-1-chris@chris-wilson.co.ukReviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
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由 Michal Wajdeczko 提交于
This function is only used by intel_guc_send() and it doesn't need to be exposed outside of intel_uc.o file. Also when defined as static, compiler will generate smaller code. Additionally let it take guc param instead dev_priv to match function name. Signed-off-by: NMichal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Reviewed-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: NTvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161220115531.76120-1-michal.wajdeczko@intel.com
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- 02 1月, 2017 2 次提交
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由 Nabendu Maiti 提交于
In future patches, we require greater flexibility in describing the number of scalers available on each CRTC. To ease that transition we move the current assignment to intel_device_info. Scaler structure initialisation is done if scaler is available on the CRTC. Gen9 check is not required as on depending upon numbers of scalers we initialize scalers or return without doing anything in skl_init_scalers. v3: Changed skl_init_scaler to intel_crtc_init_scalers v2: Added Chris's comments. Signed-off-by: NNabendu Maiti <nabendu.bikash.maiti@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2) Reviewed-by: NAnder Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480398794-22741-1-git-send-email-nabendu.bikash.maiti@intel.com
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The function intel_atomic_get_shared_dpll_state() is only called from intel_dpll_mgr.c and it concerns the same data structures as the other functions in that file, so move it there and make it static. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Suggested-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-8-git-send-email-ander.conselvan.de.oliveira@intel.com
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- 31 12月, 2016 4 次提交
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由 Chris Wilson 提交于
DRRS is not yet kerneldoc despite the allusion prior to enum drrs_refresh_rate_type. Drop the '**' to avoid the warnings from make htmldocs. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161231112012.29263-4-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
The existing kerneldoc was outdated, so time for a refresh. v2: Use single line kdoc, mention functions for manipulation Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161231112012.29263-3-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
Parameter - no. Parameter: yes. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161231112012.29263-2-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
The read of the page pin count and the bind count are unordered, presenting races in the assert and it firing off incorrectly. Prevent this by restricting the assert to the vma bind/unbind routines where we have local cpu ordering between the two. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/20161231112012.29263-1-chris@chris-wilson.co.uk
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- 30 12月, 2016 6 次提交
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Remove the IS_PLATFORM() macros from intel_dump_pipe_config() and split that logic in platform specific implementations inside the dpll code, accessed through a platform independent interface. v2: Rebase. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-7-git-send-email-ander.conselvan.de.oliveira@intel.com
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The documentation for most of the non-static members and structs were missing. Fix that. v2: Fix typos (Durga) v3: Rebase. Fix make docs warnings. Document more. v4: capitilize CRTC; say that the prepare hook is a nop if the DPLL is already enabled; link to struct intel_dpll_hw_state from @hw_state field in struct intel_shared_dpll_state; reorganize DPLL flags; link intel_shared_dpll_state to other structs and functions. (Daniel) Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-6-git-send-email-ander.conselvan.de.oliveira@intel.com
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The hook is called from intel_prepare_shared_dpll(). The name doesn't make sense after all the changes to modeset code. So just call it prepare. Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NDurgadoss R <durgadoss.r@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-5-git-send-email-ander.conselvan.de.oliveira@intel.com
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Struct intel_shared_dpll_config is used to hold the state of the DPLL in the "atomic" sense, so call it state like everything else atomic. v2: Rebase Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v1) Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-4-git-send-email-ander.conselvan.de.oliveira@intel.com
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The function intel_shared_dpll_commit() performs the equivalent of drm_atomic_helper_swap_state() for the shared dpll state, which is not handled by the helpers. So make it do a full swap of the state and rename it for consistency. v2: Fix typo in the commit message. (Durga) v3: Rebase. v4: Swap the states instead of just renaming the function. (Daniel) Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v2) Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3) Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-3-git-send-email-ander.conselvan.de.oliveira@intel.com
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While the details of getting a shared dpll are wrapped by intel_get_shared_dpll(), the release was still hand rolled into the modeset code. Fix that by creating an entry point for releasing the pll and move that code there. v2: Take old_dpll from crtc->state instead of crtc_state. (CI) Signed-off-by: NAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1483024933-3726-2-git-send-email-ander.conselvan.de.oliveira@intel.com
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- 28 12月, 2016 1 次提交
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由 Chris Wilson 提交于
Add an assertion to the plain i915_ggtt_offset() to double check that any offset we hand to the GuC is outside of its unmappable ranges. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161224193146.4402-1-chris@chris-wilson.co.ukReviewed-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
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- 26 12月, 2016 1 次提交
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
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- 24 12月, 2016 8 次提交
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由 Daniele Ceraolo Spurio 提交于
The context has to obey the same offset requirements as the ring, so we can re-use the same bias value we computed for the ring instead of unconditionally using GUC_WOPCM_TOP. Suggested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1482537382-28584-2-git-send-email-daniele.ceraolospurio@intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniele Ceraolo Spurio 提交于
GuC will validate the ring offset and fail if it is in the [0, GUC_WOPCM_TOP) range. The bias is conditionally applied only if GuC loading is enabled (we can't check for guc submission enabled as in other cases because HuC loading requires this fix). Note that the default context is processed before enable_guc_loading is sanitized, so we might still apply the bias to its ring even if it is not needed. v2: compute the value during ctx init and pass it to intel_ring_pin (Chris), updated commit message Signed-off-by: NDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1482537382-28584-1-git-send-email-daniele.ceraolospurio@intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As the fence may be signaled concurrently from an interrupt on another device, it is possible for the list of requests on the timeline to be modified as we walk it. Take both (the context's timeline and the global timeline) locks to prevent such modifications. Fixes: 80b204bc ("drm/i915: Enable multiple timelines") Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: <drm-intel-fixes@lists.freedesktop.org> Reviewed-by: NMika Kuoppala <mika.kuoppala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161223145804.6605-10-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
When creating a partial VMA assert that it first fits with the parent object, and that if it covers the whole of the parent a normal view was created instead. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161223145804.6605-5-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
As trimming the sg table is merely an optimisation that gracefully fails if we cannot allocate a new table, we do not need to report the failure either. Fixes: 0c40ce13 ("drm/i915: Trim the object sg table") Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161223145804.6605-4-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
When we teardown the backing storage for the phys object, we copy from the coherent contiguous block back to the shmemfs object, clflushing as we go. Trying to clflush the invalid sg beforehand just oops and would be redundant (due to it already being coherent, and clflushed afterwards). Reported-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: <drm-intel-fixes@lists.freedesktop.org> Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161223145804.6605-3-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
The idle work handler is self-arming - if it detects that it needs to run again it will queue itself from its work handler. Take greater care when trying to drain the idle work, and double check that it is flushed. The free worker has a similar issue where it is armed by an RCU task which may be running concurrently with us. This should hopefully help with the sporadic WARN_ON(dev_priv->gt.awake) from i915_gem_suspend. v2: Reuse drain_freed_objects. v3: Don't try to flush the freed objects from the shrinker, as it may be underneath the struct_mutex already. v4: do while and comment upon the excess rcu_barrier in drain_freed_objects Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161223145804.6605-2-chris@chris-wilson.co.uk
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由 Chris Wilson 提交于
Since commit db6c2b41 ("drm/i915: Store the vma in an rbtree under the object") the vma are once again sorted into GGTT first, then ppGTT so that the typical case of walking the GGTT vma can stop as soon as we find a non-ppGTT. Apply that optimisation. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161223145804.6605-1-chris@chris-wilson.co.uk
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- 23 12月, 2016 13 次提交
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由 Ville Syrjälä 提交于
Now that we're disabling L2 clock gating MI_OVERLAY_OFF actually works on 830, so let's use it. v2: Nuke the unused dev_priv variable Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161222195222.9618-1-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Hans de Goede 提交于
On enable intel_dsi_enable() directly calls intel_enable_dsi_pll(), make intel_dsi_disable() also directly call intel_disable_dsi_pll(), rather then hiding the call in intel_dsi_clear_device_ready(), no functional changes. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161201202925.12220-7-hdegoede@redhat.com
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由 Vincente Tsou 提交于
The upper bits of the vsync width, vsync offset and hsync width were not parsed from the VBT. Parse these fields in this patch. V2: Renamed lvds dvo timing structure members and code identation fix (Jani's review comments) V3: Corrected commit message, used "from the VBT" Signed-off-by: NVincente Tsou <vincente.tsou@intel.com> Signed-off-by: NMadhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: NJani Nikula <jani.nikula@intel.com> Signed-off-by: NJani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1482430993-3265-1-git-send-email-madhav.chauhan@intel.com
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由 Ville Syrjälä 提交于
BSpec says: "Overlay Clock Gating Must be Disabled: Overlay & L2 Cache clock gating must be disabled in order to prevent device hangs when turning off overlay.SW must turn off Ovrunit clock gating (6200h) and L2 Cache clock gating (C8h)." We only turned off the overlay clock gating (due to lack of docs I presume). After a bit of experimentation it looks like the the magic C8h register lives in the PCI config space of device 0, and the magic bit appears to be bit 2. Or at the very least this eliminates the GPU death after MI_OVERLAY_OFF. L2 clock gating seems to save ~80mW, so let's keep it on unless we need to actually use the overlay. Also let's move the OVRUNIT clock gating to the same place since we can, and 845 supposedly doesn't need it. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-11-git-send-email-ville.syrjala@linux.intel.comAcked-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
Extract the primary plane pixel format via plane state when setting up the overlay colorkey. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-10-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
Use two-dimensional arrays and named initializers to make the overlay filter coefficient tables easier to parse for humans. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-9-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
The formula in Bspec for computing the overlay SWIDTHSW is overly obfuscated. Simplify the formula to something that's easily parsed by humans. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-8-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
Check pipe config gmch_pfit.control instead of using intel_panel_fitter_pipe() to figure out if the pipe for the overlay is using the panel fitter. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-7-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
Replace the use of crtc->mode.h/vdisplay with the more appropriate config->pipe_src_w/h. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-6-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
Do the overlay frontbuffer tracking properly so that it matches the state of the overlay on/off/continue requests. One slight problem is that intel_frontbuffer_flip_complete() may get delayed by an arbitrarily liong time due to the fact that the overlay code likes to bail out when a signal occurs. So the flip may not get completed until the ioctl is restarted. But fixing that would require bigger surgery, so I decided to ignore it for now. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-5-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
The vma will be NULL if the overlay was previously off, so dereferencing it will oops. Check for NULL before doing that. Cc: stable@vger.kernel.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Fixes: 9b3b7841 ("drm/i915/overlay: Use VMA as the primary tracker for images") Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1481131693-27993-2-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Ville Syrjälä 提交于
The i915_gem_active stuff doesn't like a NULL ->retire hook, but the overlay code can set it to NULL. That obviously ends up oopsing. Fix it by introducing a new helper to assign the retirement callback that will switch out the NULL function pointer with i915_gem_retire_noop. Cc: stable@vger.kernel.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Fixes: 0d9bdd88 ("drm/i915: Convert intel_overlay to request tracking") Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/20161207175647.10018-1-chris@chris-wilson.co.uk
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由 Ville Syrjälä 提交于
Initialize overlay->last_flip properly instead of leaving it zeroed. Cc: stable@vger.kernel.org Cc: Chris Wilson <chris@chris-wilson.co.uk> Fixes: 0d9bdd88 ("drm/i915: Convert intel_overlay to request tracking") Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161221144547.27319-1-ville.syrjala@linux.intel.com
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- 22 12月, 2016 1 次提交
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由 Ville Syrjälä 提交于
Trying to determine the pixel rate of the pipe can't be done until we know the clock, which means it can't be done until the encoder .get_config() hooks have been called. So let's move the min_pixclk[] stuff to the end of intel_modeset_readout_hw_state() when we actually have gathered all the required infromation. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Fixes: 565602d7 ("drm/i915: Do not acquire crtc state to check clock during modeset, v4.") Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20161220153902.15621-1-ville.syrjala@linux.intel.comReviewed-by: NAnder Conselvan de Oliveira <conselvan2@gmail.com> Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
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