Userspace sends us a special relocation type to sync video/exa
to vlines to avoid tearing, this deals with the relocation
in the kernel, it picks the correct crtc and avoids issues
where crtcs are disabled.

This version also parses the wait until to make sure it isn't
trying to do anything evil.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Normally we are free to place VRAM where we want in the GPUs
memory address space, however on IGP chips the VRAM is actual RAM,
and no special translation or aperture is used inside the GPU MC.

So when you move the VRAM aperture away from the TOM register,
you actually move it into main memory and can trash things quite badly.

This commit makes the code respect the TOM location for MC_FB_LOCATION.
Signed-off-by: NDave Airlie <airlied@redhat.com>

The crtc and cursor offsets on the legacy chips are offset from
DISPLAY_BASE_ADDR. The code worked if display base addr was at 0,
but otherwise falls to pieces.
Signed-off-by: NDave Airlie <airlied@redhat.com>

If there is a problem then this is hiding it, we shouldn't
ever need to flush the IB. Either the buffers are:

WB - caching just works.
WC - no need to do explicit flush, the MB + readback will do it
Signed-off-by: NDave Airlie <airlied@redhat.com>

Unsigned long is incorrect for 64-bit resources on 32-bit hw.
Signed-off-by: NDave Airlie <airlied@redhat.com>

1. rv370 can accept 40-bit addresses - also at 24-bit shift not 4 bits
2. rs480 table can be in 40-bit space. - 4 bit shift for top 8 bits
3. rs480 table entries can be in 40-bit space.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Remove unused #include <linux/version.h>('s) in
 drivers/gpu/drm/ttm/ttm_bo_util.c
 drivers/gpu/drm/ttm/ttm_bo_vm.c
 drivers/gpu/drm/ttm/ttm_tt.c
Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

TTM need to be initialized before radeon if KMS is enabled otherwise
the kernel will crash hard.
Signed-off-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NDave Airlie <airlied@linux.ie>

Looks like I managed to mess up most shifts when converting from bitfields. :(

The patch below works on my Thinkpad T500 (as well as on my PowerBook,
where the previous change worked as well, maybe out of luck...). I'd
appreciate more testing and eyes looking over it though.
Signed-off-by: NMichel Dänzer <daenzer@vmware.com>
Tested-by: NMichael Pyne <mpyne@kde.org>
Signed-off-by: NDave Airlie <airlied@linux.ie>

Some PowerMac firmwares set up a tiling surface at the beginning of VRAM
which messes us up otherwise.
Signed-off-by: NMichel Dänzer <daenzer@vmware.com>
Signed-off-by: NDave Airlie <airlied@linux.ie>

Might lure userspace into trying silly things otherwise.
Signed-off-by: NMichel Dänzer <daenzer@vmware.com>
Signed-off-by: NDave Airlie <airlied@linux.ie>

smem.start is a physical address which kernel can remap to access
video memory of the fb buffer. We now pin the fb buffer into vram
by doing so we are loosing vram but fbdev need to be reworked to
allow change in framebuffer address.
Signed-off-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NDave Airlie <airlied@linux.ie>

Sometimes both acpi video and i915 driver are compiled as modules.
And there exists the strict dependency between the two drivers.
The acpi video bus will be unloaded in course of unloading the i915 driver.
If we unload the acpi video driver, then the kernel oops will be triggered.

Add the reference count to avoid unloading the ACPI video bus twice.
The reference count should be checked before unregistering the acpi video bus.
If the reference count is already zero, it won't unregister it again.
And after the acpi video bus is already unregistered, the reference count
will be set to zero.

http://bugzilla.kernel.org/show_bug.cgi?id=13396Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Acked-by: NZhang Rui <rui.zhang@intel.com>
Signed-off-by: NLen Brown <len.brown@intel.com>

Unitialized fence register could leads to corrupted display. Problem
encountered on MacBooks (revision 1 and 2), directly booting from EFI
or through BIOS emulation.

(bug #21710 at freedestop.org)
Signed-off-by: NGrégoire Henry <henry@pps.jussieu.fr>
Signed-off-by: NEric Anholt <eric@anholt.net>

Remove wrongly added NULL_PACKETS_DURING_VSYNC setting for HDMI.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Apparently the proper way to do this is to use the LFP data pointer
block to figure out the LFP data block entry size, then use that plus
the panel index to calculate an offset into the LFP data block array.

Similar fix has already been pushed to the 2D driver to fix fdo bug
applied to the VBIOS reader, and things look sane).
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

We used load_detect_temp flag to determine whether to set tv to the test
mode. However if the TV already has a mode set, we still need to set the
test mode to determine connection.  This results in blinking, but there is
no other reliable way to determine TV connection.

freedesktop.org bug #22035
Signed-off-by: NMa Ling <ling.ma@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NKrzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NKrzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: NEric Anholt <eric@anholt.net>

Also, use the border instead of border minus one.

At the same time, make sure the horizontal border and hsync are even for
the LVDS that works in dual-channel mode. So both horizontal border and hsync
start are also changed to be even, even for the LVDS in single-channel mode.

https://bugs.freedesktop.org/show_bug.cgi?id=20951Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Previously the driver would always scale the chosen video mode to fill the
panel.  This adds 1:1 and maintain-aspect-ratio scaling modes.

v2: the drm_calloc/drm_free is replaced by kzalloc/kfree based
on Eric's suggestion.
Signed-off-by: NZhao Yakui <yakui.zhao@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

We need to save register state *after* idling GEM, clearing the ring,
and uninstalling the IRQ handler, or we might end up saving bogus
fence regs, for one.  Our restore ordering should already be correct,
since we do GEM, ring and IRQ init after restoring the last register
state, which prevents us from clobbering things.

I put this together to potentially address a bug, but I haven't heard
back if it fixes it yet.  However I think it stands on its own, so I'm
sending it in.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

Users could accidentally enable AGP but not the Intel AGP support, and get
a DRM that doesn't probe as a result.

Bug #22358.
Signed-off-by: NEric Anholt <eric@anholt.net>

In theory now that the AGP subsystem is using struct page, we should
have on problems enabling GEM on PAE systems.
Signed-off-by: NDave Airlie <airlied@redhat.com>

just remove i variable left over from previous code.
Signed-off-by: NDave Airlie <airlied@redhat.com>

This switches AGP to use an array of pages for tracking the
pages allocated to the GART. This should enable GEM on PAE to work
a lot better as we can pass highmem pages to the PAT code and it will
do the right thing with them.
Signed-off-by: NDave Airlie <airlied@redhat.com>

For security purpose we want to make sure the userspace process doesn't
access memory beyond buffer it owns. To achieve this we need to check
states the userspace program. For color buffer and zbuffer we check that
the clipping register will discard access beyond buffers set as color
or zbuffer. For vertex buffer we check that no vertex fetch will happen
beyond buffer end. For texture we check various texture states (number
of mipmap level, texture size, texture depth, ...) to compute the amount
of memory the texture fetcher might access.

The command stream checking impact the performances so far quick benchmark
shows an average of 3% decrease in fps of various applications. It can
be optimized a bit more by caching result of checking and thus avoid a
full recheck if no states changed since last check.

Note that this patch is still incomplete on checking side as it doesn't
check 2d rendering states.
Signed-off-by: NJerome Glisse <jglisse@redhat.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

This makes the panel on my PowerBook light up.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Signed-off-by: NDave Airlie <airlied@redhat.com>

Optimise the powerpc flushing path for TTM.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Signed-off-by: NDave Airlie <airlied@redhat.com>

Some AGP devices can't map the aperture, radeon needs to tell TTM this.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Mostly replacing bitfields with explicit masks and shifts.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Its quite valid to have VRAM < aperture size.
Signed-off-by: NDave Airlie <airlied@redhat.com>

Just a goto instead of a direct exit.
Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

also for the atomic path by using a common code-path.
Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

A bug caused the ttm code to just terminate the wait when a signal
was received while waiting for the GPU to release a buffer object that
was to be evicted.
Signed-off-by: NThomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

The display port aux channel clock is taken from the hrawclk value, which is
provided to the chip as the FSB frequency (as far as I can determine). The
strapping values for that are available in the CLKCFG register, now used to
select an appropriate divider to generate a 2MHz clock.

In addition, the DisplayPort spec requires that each aux channel I/O be
retried 'at least 3 times' in case the sink is idle when the first request
comes in.
Signed-off-by: NKeith Packard <keithp@keithp.com>

Use distinct error return values for each kind of aux channel I/O failure.
Signed-off-by: NKeith Packard <keithp@keithp.com>

The CLKCFG register holds information about the GMCH plls and input clock
values.
Signed-off-by: NKeith Packard <keithp@keithp.com>