- 14 2月, 2013 2 次提交
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由 Laxman Dewangan 提交于
Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
enum tegra*_clk is intended to match the IDs listed in the Tegra clock bindings. There are a few mismatches, which this patch fixes: 1) pll_s and cop were left out of the Tegra20 enum. 2) spdif_in and spdif_out were swapped relative to the Tegra30 binding. 3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added to the Tegra30 enum. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de> Tested-by: NThierry Reding <thierry.reding@avionic-design.de>
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- 13 2月, 2013 3 次提交
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由 Peter De Schrijver 提交于
cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within clk-tegra30.c. Declare them static to avoid namespace polution. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Peter De Schrijver 提交于
The hclk and pclk clocks are controlled by the same register. Hence a lock is required to avoid corruption. Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The index of se should be 127. And the previous clock index was 125. So we need to set up the index for se to get the correct index between se to sata_cold. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 29 1月, 2013 2 次提交
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由 Prashant Gaikwad 提交于
With device tree support added for Tegra clocks look up is done from device tree, remove unused TEGRA_CLK_DUPLICATE()s. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Prashant Gaikwad 提交于
Add Tegra30 clock support based on common clock framework. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: ensure all OF lookups return valid cookies i.e. an explicit error pointer or valid pointer not NULL, adapt to renames in earlier patches, fixed some checkpatch issues.] Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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