1. 15 2月, 2017 5 次提交
    • M
      arm64: cpufeature: correctly handle MRS to XZR · 521c6461
      Mark Rutland 提交于
      In emulate_mrs() we may erroneously write back to the user SP rather
      than XZR if we trap an MRS instruction where Xt == 31.
      
      Use the new pt_regs_write_reg() helper to handle this correctly.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Fixes: 77c97b4e ("arm64: cpufeature: Expose CPUID registers by emulation")
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      521c6461
    • M
      arm64: traps: correctly handle MRS/MSR with XZR · 8b6e70fc
      Mark Rutland 提交于
      Currently we hand-roll XZR-safe register handling in
      user_cache_maint_handler(), though we forget to do the same in
      ctr_read_handler(), and may erroneously write back to the user SP rather
      than XZR.
      
      Use the new helpers to handle these cases correctly and consistently.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Fixes: 116c81f4 ("arm64: Work around systems with mismatched cache line sizes")
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      8b6e70fc
    • M
      arm64: ptrace: add XZR-safe regs accessors · 6c23e2ff
      Mark Rutland 提交于
      In A64, XZR and the SP share the same encoding (31), and whether an
      instruction accesses XZR or SP for a particular register parameter
      depends on the definition of the instruction.
      
      We store the SP in pt_regs::regs[31], and thus when emulating
      instructions, we must be careful to not erroneously read from or write
      back to the saved SP. Unfortunately, we often fail to be this careful.
      
      In all cases, instructions using a transfer register parameter Xt use
      this to refer to XZR rather than SP. This patch adds helpers so that we
      can more easily and consistently handle these cases.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      6c23e2ff
    • A
      arm64: include asm/assembler.h in entry-ftrace.S · f705d954
      Arnd Bergmann 提交于
      In a randconfig build I ran into this build error:
      
      arch/arm64/kernel/entry-ftrace.S: Assembler messages:
      arch/arm64/kernel/entry-ftrace.S:101: Error: unknown mnemonic `ldr_l' -- `ldr_l x2,ftrace_trace_function'
      
      The macro is defined in asm/assembler.h, so we should include that file.
      
      Fixes: 829d2bd1 ("arm64: entry-ftrace.S: avoid open-coded {adr,ldr}_l")
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f705d954
    • A
      arm64: fix warning about swapper_pg_dir overflow · 12f043ff
      Arnd Bergmann 提交于
      With 4 levels of 16KB pages, we get this warning about the fact that we are
      copying a whole page into an array that is declared as having only two pointers
      for the top level of the page table:
      
      arch/arm64/mm/mmu.c: In function 'paging_init':
      arch/arm64/mm/mmu.c:528:2: error: 'memcpy' writing 16384 bytes into a region of size 16 overflows the destination [-Werror=stringop-overflow=]
      
      This is harmless since we actually reserve a whole page in the definition of the
      array that comes from, and just the extern declaration is short. The pgdir
      is initialized to zero either way, so copying the actual entries here seems
      like the best solution.
      Acked-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      12f043ff
  2. 10 2月, 2017 3 次提交
    • C
      arm64: Work around Falkor erratum 1003 · 38fd94b0
      Christopher Covington 提交于
      The Qualcomm Datacenter Technologies Falkor v1 CPU may allocate TLB entries
      using an incorrect ASID when TTBRx_EL1 is being updated. When the erratum
      is triggered, page table entries using the new translation table base
      address (BADDR) will be allocated into the TLB using the old ASID. All
      circumstances leading to the incorrect ASID being cached in the TLB arise
      when software writes TTBRx_EL1[ASID] and TTBRx_EL1[BADDR], a memory
      operation is in the process of performing a translation using the specific
      TTBRx_EL1 being written, and the memory operation uses a translation table
      descriptor designated as non-global. EL2 and EL3 code changing the EL1&0
      ASID is not subject to this erratum because hardware is prohibited from
      performing translations from an out-of-context translation regime.
      
      Consider the following pseudo code.
      
        write new BADDR and ASID values to TTBRx_EL1
      
      Replacing the above sequence with the one below will ensure that no TLB
      entries with an incorrect ASID are used by software.
      
        write reserved value to TTBRx_EL1[ASID]
        ISB
        write new value to TTBRx_EL1[BADDR]
        ISB
        write new value to TTBRx_EL1[ASID]
        ISB
      
      When the above sequence is used, page table entries using the new BADDR
      value may still be incorrectly allocated into the TLB using the reserved
      ASID. Yet this will not reduce functionality, since TLB entries incorrectly
      tagged with the reserved ASID will never be hit by a later instruction.
      
      Based on work by Shanker Donthineni <shankerd@codeaurora.org>
      Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NChristopher Covington <cov@codeaurora.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      38fd94b0
    • W
      arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 · 2bf47e19
      Will Deacon 提交于
      The SPE architecture requires each exception level to enable access
      to the SPE controls for the exception level below it, since additional
      context-switch logic may be required to handle the buffer safely.
      
      This patch allows EL1 (host) access to the SPE controls when entered at
      EL2.
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      2bf47e19
    • D
      arm64: arch_timer: document Hisilicon erratum 161010101 · 6e01398f
      Ding Tianhong 提交于
      Now that we have a workaround for Hisilicon erratum 161010101, notes
      this in the arm64 silicon-errata document.
      
      The new config option is too long to fit in the existing kconfig column,
      so this is widened to accomodate it. At the same time, an existing
      whitespace error is corrected, and the existing pattern of a line space
      between vendors is enforced for recent additions.
      Signed-off-by: NDing Tianhong <dingtianhong@huawei.com>
      [Mark: split patch, reword commit message, rework table]
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      6e01398f
  3. 09 2月, 2017 4 次提交
  4. 08 2月, 2017 2 次提交
  5. 07 2月, 2017 4 次提交
    • P
      arm64: do not trace atomic operations · b7eed6dd
      Pratyush Anand 提交于
      Atomic operation function symbols are exported,when
      CONFIG_ARM64_LSE_ATOMICS is defined. Prefix them with notrace, so that
      an user can not trace these functions. Tracing these functions causes
      kernel crash.
      Signed-off-by: NPratyush Anand <panand@redhat.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      b7eed6dd
    • D
      ACPI/IORT: Fix the error return code in iort_add_smmu_platform_device() · 5e5afa6c
      Dan Carpenter 提交于
      The function iort_add_smmu_platform_device() accidentally returns 0
      (ie PTR_ERR(pdev) where pdev == NULL) if platform_device_alloc() fails;
      fix the bug by returning a proper error value.
      
      Fixes: 846f0e9e ("ACPI/IORT: Add support for ARM SMMU platform devices creation")
      Acked-by: NHanjun Guo <hanjun.guo@linaro.org>
      Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
      [lorenzo.pieralisi@arm.com: improved commit log]
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      5e5afa6c
    • L
      ACPI/IORT: Fix iort_node_get_id() mapping entries indexing · 030abd8a
      Lorenzo Pieralisi 提交于
      Commit 618f535a ("ACPI/IORT: Add single mapping function")
      introduced a function (iort_node_get_id()) to retrieve ids for IORT
      named components.
      
      The iort_node_get_id() takes an index as input to refer to a specific
      mapping entry in the named component IORT node mapping array.
      
      For a mapping entry at a given index, iort_node_get_id() should return
      the id value (through the id_out function parameter) and the IORT node
      output_reference (through function return value) the given mapping entry
      refers to.
      
      Technically output_reference values may differ for different map
      entries, (see diagram below - mapped id values may refer to different eg
      IORT SMMU nodes; the kernel may not be able to handle different
      output_reference values for a given named component but the IORT kernel
      layer should still report the IORT mappings as reported by firmware) but
      current code in iort_node_get_id() fails to use the index function
      parameter to return the correct output_reference value (ie it always
      returns the output_reference value of the first entry in the mapping
      array whilst using the index correctly to retrieve the id value from the
      respective entry).
      
      	|----------------------|
      	|     named component  |
      	|----------------------|
      	|      map entry[0]    |
      	|----------------------|
      	|       id value       |
      	| output_reference----------------> eg SMMU 1
      	|----------------------|
      	|      map entry[1]    |
      	|----------------------|
      	|       id value       |
      	| output_reference----------------> eg SMMU 2
      	|----------------------|
      		    .
      		    .
      		    .
      	|----------------------|
      	|      map entry[N]    |
      	|----------------------|
      	|       id value       |
      	| output_reference----------------> eg SMMU 1
      	|----------------------|
      
      Consequently the iort_node_get_id() function always returns the IORT
      node pointed at by the output_reference value of the first named
      component mapping array entry, irrespective of the index parameter,
      which is a bug.
      
      Update the map array entry pointer computation in iort_node_get_id() to
      take into account the index value, fixing the issue.
      
      Fixes: 618f535a ("ACPI/IORT: Add single mapping function")
      Reported-by: NHanjun Guo <hanjun.guo@linaro.org>
      Reviewed-by: NHanjun Guo <hanjun.guo@linaro.org>
      Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Hanjun Guo <hanjun.guo@linaro.org>
      Cc: Sinan Kaya <okaya@codeaurora.org>
      Cc: Tomasz Nowicki <tn@semihalf.com>
      Cc: Nate Watterson <nwatters@codeaurora.org>
      Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      030abd8a
    • A
      arm64: mm: enable CONFIG_HOLES_IN_ZONE for NUMA · 6d526ee2
      Ard Biesheuvel 提交于
      The NUMA code may get confused by the presence of NOMAP regions within
      zones, resulting in spurious BUG() checks where the node id deviates
      from the containing zone's node id.
      
      Since the kernel has no business reasoning about node ids of pages it
      does not own in the first place, enable CONFIG_HOLES_IN_ZONE to ensure
      that such pages are disregarded.
      Acked-by: NRobert Richter <rrichter@cavium.com>
      Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      6d526ee2
  6. 04 2月, 2017 4 次提交
  7. 03 2月, 2017 5 次提交
    • A
      efi: arm64: Add vmlinux debug link to the Image binary · 757b435a
      Ard Biesheuvel 提交于
      When building with debugging symbols, take the absolute path to the
      vmlinux binary and add it to the special PE/COFF debug table entry.
      This allows a debug EFI build to find the vmlinux binary, which is
      very helpful in debugging, given that the offset where the Image is
      first loaded by EFI is highly unpredictable.
      
      On implementations of UEFI that choose to implement it, this
      information is exposed via the EFI debug support table, which is a UEFI
      configuration table that is accessible both by the firmware at boot time
      and by the OS at runtime, and lists all PE/COFF images loaded by the
      system.
      
      The format of the NB10 Codeview entry is based on the definition used
      by EDK2, which is our primary reference when it comes to the use of
      PE/COFF in the context of UEFI firmware.
      Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      [will: use realpath instead of shell invocation, as discussed on list]
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      757b435a
    • M
      arm64: ensure __raw_read_system_reg() is self-consistent · 965861d6
      Mark Rutland 提交于
      We recently discovered that __raw_read_system_reg() erroneously mapped
      sysreg IDs to the wrong registers.
      
      To ensure that we don't get hit by a similar issue in future, this patch
      makes __raw_read_system_reg() use a macro for each case statement,
      ensuring that each case reads the correct register.
      
      To ensure that this patch hasn't introduced an issue, I've binary-diffed
      the object files before and after this patch. No code or data sections
      differ (though some debug section differ due to line numbering
      changing).
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      965861d6
    • M
      arm64: fix erroneous __raw_read_system_reg() cases · 7d0928f1
      Mark Rutland 提交于
      Since it was introduced in commit da8d02d1 ("arm64/capabilities:
      Make use of system wide safe value"), __raw_read_system_reg() has
      erroneously mapped some sysreg IDs to other registers.
      
      For the fields in ID_ISAR5_EL1, our local feature detection will be
      erroneous. We may spuriously detect that a feature is uniformly
      supported, or may fail to detect when it actually is, meaning some
      compat hwcaps may be erroneous (or not enforced upon hotplug).
      
      This patch corrects the erroneous entries.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Fixes: da8d02d1 ("arm64/capabilities: Make use of system wide safe value")
      Reported-by: NCatalin Marinas <catalin.marinas@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: stable@vger.kernel.org
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      7d0928f1
    • W
      arm64: KVM: Save/restore the host SPE state when entering/leaving a VM · f85279b4
      Will Deacon 提交于
      The SPE buffer is virtually addressed, using the page tables of the CPU
      MMU. Unusually, this means that the EL0/1 page table may be live whilst
      we're executing at EL2 on non-VHE configurations. When VHE is in use,
      we can use the same property to profile the guest behind its back.
      
      This patch adds the relevant disabling and flushing code to KVM so that
      the host can make use of SPE without corrupting guest memory, and any
      attempts by a guest to use SPE will result in a trap.
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: Alex Bennée <alex.bennee@linaro.org>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f85279b4
    • D
      arm64: make use of for_each_node_by_type() · 3d29a9a0
      Dmitry Torokhov 提交于
      Instead of open-coding the loop, let's use canned macro.
      Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      3d29a9a0
  8. 01 2月, 2017 2 次提交
    • C
      arm64: Work around Falkor erratum 1009 · d9ff80f8
      Christopher Covington 提交于
      During a TLB invalidate sequence targeting the inner shareable domain,
      Falkor may prematurely complete the DSB before all loads and stores using
      the old translation are observed. Instruction fetches are not subject to
      the conditions of this erratum. If the original code sequence includes
      multiple TLB invalidate instructions followed by a single DSB, onle one of
      the TLB instructions needs to be repeated to work around this erratum.
      While the erratum only applies to cases in which the TLBI specifies the
      inner-shareable domain (*IS form of TLBI) and the DSB is ISH form or
      stronger (OSH, SYS), this changes applies the workaround overabundantly--
      to local TLBI, DSB NSH sequences as well--for simplicity.
      
      Based on work by Shanker Donthineni <shankerd@codeaurora.org>
      Signed-off-by: NChristopher Covington <cov@codeaurora.org>
      Acked-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      d9ff80f8
    • C
      arm64: Improve detection of user/non-user mappings in set_pte(_at) · ec663d96
      Catalin Marinas 提交于
      Commit cab15ce6 ("arm64: Introduce execute-only page access
      permissions") allowed a valid user PTE to have the PTE_USER bit clear.
      As a consequence, the pte_valid_not_user() macro in set_pte() was
      replaced with pte_valid_global() under the assumption that only user
      pages have the nG bit set. EFI mappings, however, also have the nG bit
      set and set_pte() wrongly ignores issuing the DSB+ISB.
      
      This patch reinstates the pte_valid_not_user() macro and adds the
      PTE_UXN bit check since all kernel mappings have this bit set. For
      clarity, pte_exec() is renamed to pte_user_exec() as it only checks for
      the absence of PTE_UXN. Consequently, the user executable check in
      set_pte_at() drops the pte_ng() test since pte_user_exec() is
      sufficient.
      
      Fixes: cab15ce6 ("arm64: Introduce execute-only page access permissions")
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      ec663d96
  9. 28 1月, 2017 1 次提交
    • M
      arm64: handle sys and undef traps consistently · 49f6cba6
      Mark Rutland 提交于
      If an EL0 instruction in the SYS class triggers an exception, do_sysintr
      looks for a sys64_hook matching the instruction, and if none is found,
      injects a SIGILL. This mirrors what we do for undefined instruction
      encodings in do_undefinstr, where we look for an undef_hook matching the
      instruction, and if none is found, inject a SIGILL.
      
      Over time, new SYS instruction encodings may be allocated. Prior to
      allocation, exceptions resulting from these would be handled by
      do_undefinstr, whereas after allocation these may be handled by
      do_sysintr.
      
      To ensure that we have consistent behaviour if and when this happens, it
      would be beneficial to have do_sysinstr fall back to do_undefinstr.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
      Reviewed-by: NSuzuki Poulose <suzuki.poulose@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      49f6cba6
  10. 27 1月, 2017 2 次提交
  11. 26 1月, 2017 5 次提交
  12. 23 1月, 2017 1 次提交
  13. 18 1月, 2017 2 次提交
    • M
      arm64: entry-ftrace.S: avoid open-coded {adr,ldr}_l · 829d2bd1
      Mark Rutland 提交于
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of these in entry-ftrace.S, removing open-coded
      sequences using adrp. This results in a minor code change, since a
      temporary register is not used when generating the address for some
      symbols, but this is fine, as the value of the temporary register is not
      used elsewhere.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reviewed-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      829d2bd1
    • M
      arm64: efi-entry.S: avoid open-coded adr_l · 526d10ae
      Mark Rutland 提交于
      Some places in the kernel open-code sequences using ADRP for a symbol
      another instruction using a :lo12: relocation for that same symbol.
      These sequences are easy to get wrong, and more painful to read than is
      necessary. For these reasons, it is preferable to use the
      {adr,ldr,str}_l macros for these cases.
      
      This patch makes use of these in efi-entry.S, removing open-coded
      sequences using adrp.
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Reviewed-by: NArd Biesheuvel <ard.biesheuvel@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Matt Fleming <matt@codeblueprint.co.uk>
      Cc: Will Deacon <will.deacon@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      526d10ae