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  1. 04 11月, 2017 2 次提交
  3. 20 10月, 2017 1 次提交
  5. 04 10月, 2017 6 次提交
  7. 19 9月, 2017 1 次提交
  9. 29 8月, 2017 2 次提交
  11. 30 7月, 2017 1 次提交
  13. 17 7月, 2017 2 次提交
  15. 29 6月, 2017 3 次提交
  17. 25 5月, 2017 1 次提交
  19. 18 5月, 2017 1 次提交
  21. 12 4月, 2017 1 次提交
  23. 09 4月, 2017 1 次提交
  25. 31 1月, 2017 2 次提交
    • F
      serial: imx: Fix the CTS_B polarity in RS485 mode · bc2be239
      由 Fabio Estevam 提交于 
      When userspace passes the SER_RS485_RTS_ON_SEND flag it means that the
CTS_B pin should go to logic level high before the transmission begins.

CTS_B goes to logic level high when both CTSC and CTS bits are cleared.

When userspace passes the SER_RS485_RTS_AFTER_SEND flag it means that the
CTS_B pin should go to logic level low after the transmission finishes.

CTS_B goes to logic level low when CTSC bit is cleared and CTS bit is set.

So fix the CTS_B polarity logic.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      bc2be239
    • F
      serial: imx: Fix the RTS GPIO polarity in RS485 mode · 1a613626
      由 Fabio Estevam 提交于 
      On a board that needs to drive RTS GPIO high in order to enable the
transmission of a RS485 transceiver the following description is
passed in the devide tree:

&uart4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart4>;
        rts-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
        status = "okay";
};

and userspace configures the uart port as follows:

/* enable RS485 mode: */
rs485conf.flags |= SER_RS485_ENABLED;

/* set logical level for RTS pin equal to 1 when sending: */
rs485conf.flags |= SER_RS485_RTS_ON_SEND;

/* set logical level for RTS pin equal to 0 after sending: */
rs485conf.flags &= ~(SER_RS485_RTS_AFTER_SEND);

However the RTS GPIO polarity observed in the oscilloscope is inverted.

When the SER_RS485_RTS_ON_SEND flag is set the imx_port_rts_active()
function should be called and following the same logic when
SER_RS485_RTS_AFTER_SEND flag is cleared the imx_port_rts_inactive()
should be called.

Do such logic change so that RS485 communication in half duplex can
work successfully when the RTS GPIO pin is passed via device tree.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      1a613626
  27. 12 1月, 2017 1 次提交
  29. 27 9月, 2016 1 次提交
  31. 15 9月, 2016 1 次提交
  33. 14 9月, 2016 1 次提交
  35. 02 9月, 2016 2 次提交
  37. 31 8月, 2016 2 次提交
    • N
      serial: imx-serial - update RX error counters when DMA is used · 41d98b5d
      由 Nandor Han 提交于 
      Update error counters when DMA is used for receiving data. Do
this by using DMA transaction error event instead error interrupts
to reduce interrupt load.
Tested-by: NPeter Senna Tschudin <peter.senna@collabora.com>
Acked-by: NPeter Senna Tschudin <peter.senna@collabora.com>
Signed-off-by: NNandor Han <nandor.han@ge.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      41d98b5d
    • N
      serial: imx-serial - update UART IMX driver to use cyclic DMA · 9d297239
      由 Nandor Han 提交于 
      The IMX UART has a 32 bytes HW buffer which can be filled up in
2777us at 115200 baud or 80us at 4Mbaud (supported by IMX53).
Taking this in consideration there is a good probability to lose
data because of the DMA startup latency.
Our tests (explained below) indicates a latency up to 4400us when
creating interrupt load and ~70us without. When creating interrupt
load I was able to see continuous overrun errors by checking serial
driver statistics using the command:
`cat /proc/tty/driver/IMX-uart`.

Replace manual restart of DMA with cyclic DMA to eliminate data loss
due to DMA engine startup latency (similar approch to atmel_serial.c
driver). As result the DMA engine will start on the first serial data
transfer and stops only when serial port is closed.

Tests environment:
 Using the m53evk board I have used a GPIO for profiling the IMX
 serial driver.
  - The RX line and GPIO were connected to oscilloscope.
  - Run a small test program on the m53evk board that will only open
    and read data from ttymxc2 port.
  - Connect the ttymxc2 port to my laptop using a USB serial converter
    where another test program is running, able to send configurable
    packet lengths and intervals.
  - Serial ports configured at 115200 8N1.
  - Interrupts load created by disconnecting/connecting (3s interval)
    a USB hub, using a digital switch, with 4 USB devices (USB-Serial
    converter, USB SD card, etc) connected.
    (around 160 interrupts/second generated)
  - The GPIO was toggled HI in the `imx_int` when USR1_RRDY or USR1_AGTIM
    events are received and toggled back, once the DMA configuration
    is finalized, at the end of `imx_dma_rxint`.

Measurements:
The measurements were done from the end of the last byte (RX line) until
the GPIO was toggled back LOW.

Note: The GPIO toggling was done using `gpiod_set_value` method.

Tests performed:
   1. Sending 9 bytes packets at 8ms interval. Having the 9 bytes packets
      will activate the RRDY threshold event and IMX serial interrupt
      called.
      Results:
        - DMA start latency (interrupt start latency +
           DMA configuration) consistently 70us when system not loaded.
        - DMA start latency up to 4400us when system loaded.
   2. Sending 40 bytes packet at 8mS interval.
      Results with load:
        - Able to observe overruns by running:
           `watch -n1 cat /proc/tty/driver/IMX-uart`
Tested-by: NPeter Senna Tschudin <peter.senna@collabora.com>
Acked-by: NPeter Senna Tschudin <peter.senna@collabora.com>
Signed-off-by: NNandor Han <nandor.han@ge.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      9d297239
  39. 01 5月, 2016 8 次提交