- 21 9月, 2007 1 次提交
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由 Magnus Damm 提交于
This patch adds single bitmap register support to intc. The current code only handles 16 and 32 bit registers where a set bit means interrupt enabled, but this is easy to extend in the future. The INTC_IRQ() macro is also added to provide a way to hook in interrupt controllers for FPGAs in boards or companion chips. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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- 20 7月, 2007 2 次提交
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由 Magnus Damm 提交于
This patch improves intc group support, ie it makes it possible to group interrupts together and mask / unmask the entire group. This also works with priorities, so setting a priority for an entire group is also possible. This patch is needed to properly support certain processors such as the 7780. Fixes for NULL pointers in DECLARE_INTC_DESC() are also included. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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由 Magnus Damm 提交于
This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: NMagnus Damm <damm@igel.co.jp> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
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