1. 04 5月, 2012 1 次提交
  2. 11 4月, 2012 1 次提交
  3. 25 2月, 2012 1 次提交
  4. 22 2月, 2012 1 次提交
    • S
      USB: Fix handoff when BIOS disables host PCI device. · cab928ee
      Sarah Sharp 提交于
      On some systems with an Intel Panther Point xHCI host controller, the
      BIOS disables the xHCI PCI device during boot, and switches the xHCI
      ports over to EHCI.  This allows the BIOS to access USB devices without
      having xHCI support.
      
      The downside is that the xHCI BIOS handoff mechanism will fail because
      memory mapped I/O is not enabled for the disabled PCI device.
      Jesse Barnes says this is expected behavior.  The PCI core will enable
      BARs before quirks run, but it will leave it in an undefined state, and
      it may not have memory mapped I/O enabled.
      
      Make the generic USB quirk handler call pci_enable_device() to re-enable
      MMIO, and call pci_disable_device() once the host-specific BIOS handoff
      is finished.  This will balance the ref counts in the PCI core.  When
      the PCI probe function is called, usb_hcd_pci_probe() will call
      pci_enable_device() again.
      
      This should be back ported to kernels as old as 2.6.31.  That was the
      first kernel with xHCI support, and no one has complained about BIOS
      handoffs failing due to memory mapped I/O being disabled on other hosts
      (EHCI, UHCI, or OHCI).
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Acked-by: NOliver Neukum <oneukum@suse.de>
      Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
      Cc: stable@vger.kernel.org
      cab928ee
  5. 03 2月, 2012 1 次提交
  6. 19 11月, 2011 1 次提交
    • A
      OHCI: final fix for NVIDIA problems (I hope) · c6187597
      Alan Stern 提交于
      Problems with NVIDIA's OHCI host controllers persist.  After looking
      carefully through the spec, I finally realized that when a controller
      is reset it then automatically goes into a SUSPEND state in which it
      is completely quiescent (no DMA and no IRQs) and from which it will
      not awaken until the system puts it into the OPERATIONAL state.
      
      Therefore there's no need to worry about controllers being in the
      RESET state for extended periods, or remaining in the OPERATIONAL
      state during system shutdown.  The proper action for device
      initialization is to put the controller into the RESET state (if it's
      not there already) and then to issue a software reset.  Similarly, the
      proper action for device shutdown is simply to do a software reset.
      
      This patch (as1499) implements such an approach.  It simplifies
      initialization and shutdown, and allows the NVIDIA shutdown-quirk code
      to be removed.
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Tested-by: NAndre "Osku" Schmidt <andre.osku.schmidt@googlemail.com>
      Tested-by: NArno Augustin <Arno.Augustin@web.de>
      Cc: stable <stable@vger.kernel.org> [after tested in 3.2 for a while]
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      c6187597
  7. 15 11月, 2011 1 次提交
  8. 01 11月, 2011 1 次提交
  9. 09 8月, 2011 1 次提交
    • A
      usb/host/pci-quirks.c: correct annotation of `ehci_dmi_nohandoff_table' · a7e6401e
      Arnaud Lacombe 提交于
      ehci_bios_handoff() is marked __devinit, `ehci_dmi_nohandoff_table' should be
      marked __devinitconst, not __initconst. This fixes the following section
      mismatch:
      
      WARNING: vmlinux.o(.devinit.text+0x4f08): Section mismatch in reference from the function ehci_bios_handoff() to the variable .init.rodata:ehci_dmi_nohandoff_table
      The function __devinit ehci_bios_handoff() references a variable __initconst ehci_dmi_nohandoff_table.
      If ehci_dmi_nohandoff_table is only used by ehci_bios_handoff then annotate ehci_dmi_nohandoff_table with a matching annotation.
      
      Cc: Sarah Sharp <sarah.a.sharp@linux.intel.com>
      Signed-off-by: NArnaud Lacombe <lacombar@gmail.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      a7e6401e
  10. 02 8月, 2011 1 次提交
  11. 16 7月, 2011 1 次提交
    • A
      USB: OHCI: fix another regression for NVIDIA controllers · 6ea12a04
      Alan Stern 提交于
      The NVIDIA series of OHCI controllers continues to be troublesome.  A
      few people using the MCP67 chipset have reported that even with the
      most recent kernels, the OHCI controller fails to handle new
      connections and spams the system log with "unable to enumerate USB
      port" messages.  This is different from the other problems previously
      reported for NVIDIA OHCI controllers, although it is probably related.
      
      It turns out that the MCP67 controller does not like to be kept in the
      RESET state very long.  After only a few seconds, it decides not to
      work any more.  This patch (as1479) changes the PCI initialization
      quirk code so that NVIDIA controllers are switched into the SUSPEND
      state after 50 ms of RESET.  With no interrupts enabled and all the
      downstream devices reset, and thus unable to send wakeup requests,
      this should be perfectly safe (even for non-NVIDIA hardware).
      
      The removal code in ohci-hcd hasn't been changed; it will still leave
      the controller in the RESET state.  As a result, if someone unloads
      ohci-hcd and then reloads it, the controller won't work again until
      the system is rebooted.  If anybody complains about this, the removal
      code can be updated similarly.
      
      This fixes Bugzilla #22052.
      Tested-by: NLarry Finger <Larry.Finger@lwfinger.net>
      Cc: stable <stable@kernel.org>
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      6ea12a04
  12. 09 7月, 2011 2 次提交
  13. 28 5月, 2011 1 次提交
    • S
      Intel xhci: Support EHCI/xHCI port switching. · 69e848c2
      Sarah Sharp 提交于
      The Intel Panther Point chipsets contain an EHCI and xHCI host controller
      that shares some number of skew-dependent ports.  These ports can be
      switched from the EHCI to the xHCI host (and vice versa) by a hardware MUX
      that is controlled by registers in the xHCI PCI configuration space.  The
      USB 3.0 SuperSpeed terminations on the xHCI ports can be controlled
      separately from the USB 2.0 data wires.
      
      This switchover mechanism is there to support users who do a custom
      install of certain non-Linux operating systems that don't have official
      USB 3.0 support.  By default, the ports are under EHCI, SuperSpeed
      terminations are off, and USB 3.0 devices will show up under the EHCI
      controller at reduced speeds.  (This was more palatable for the marketing
      folks than having completely dead USB 3.0 ports if no xHCI drivers are
      available.)  Users should be able to turn on xHCI by default through a
      BIOS option, but users are happiest when they don't have to change random
      BIOS settings.
      
      This patch introduces a driver method to switchover the ports from EHCI to
      xHCI before the EHCI driver finishes PCI enumeration.  We want to switch
      the ports over before the USB core has the chance to enumerate devices
      under EHCI, or boot from USB mass storage will fail if the boot device
      connects under EHCI first, and then gets disconnected when the port
      switches over to xHCI.
      
      Add code to the xHCI PCI quirk to switch the ports from EHCI to xHCI.  The
      PCI quirks code will run before any other PCI probe function is called, so
      this avoids the issue with boot devices.
      
      Another issue is with BIOS behavior during system resume from hibernate.
      If the BIOS doesn't support xHCI, it may switch the devices under EHCI to
      allow use of the USB keyboard, mice, and mass storage devices.  It's
      supposed to remember the value of the port routing registers and switch
      them back when the OS attempts to take control of the xHCI host controller,
      but we all know not to trust BIOS writers.
      
      Make both the xHCI driver and the EHCI driver attempt to switchover the
      ports in their PCI resume functions.  We can't guarantee which PCI device
      will be resumed first, so this avoids any race conditions.  Writing a '1'
      to an already set port switchover bit or a '0' to a cleared port switchover
      bit should have no effect.
      
      The xHCI PCI configuration registers will be documented in the EDS-level
      chipset spec, which is not public yet.  I have permission from legal and
      the Intel chipset group to release this patch early to allow good Linux
      support at product launch.  I've tried to document the registers as much
      as possible, so please let me know if anything is unclear.
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      69e848c2
  14. 13 5月, 2011 2 次提交
  15. 14 4月, 2011 1 次提交
    • J
      USB host: Fix lockdep warning in AMD PLL quirk · 9ab7927b
      Joerg Roedel 提交于
      Booting latest kernel on my test machine produces a lockdep
      warning from the usb_amd_find_chipset_info() function:
      
       WARNING: at /data/lemmy/linux.trees.git/kernel/lockdep.c:2465 lockdep_trace_alloc+0x95/0xc2()
       Hardware name: Snook
       Modules linked in:
       Pid: 959, comm: work_for_cpu Not tainted 2.6.39-rc2+ #22
       Call Trace:
        [<ffffffff8103c0d4>] warn_slowpath_common+0x80/0x98
        [<ffffffff812387e6>] ? T.492+0x24/0x26
        [<ffffffff8103c101>] warn_slowpath_null+0x15/0x17
        [<ffffffff81068667>] lockdep_trace_alloc+0x95/0xc2
        [<ffffffff810ed9ac>] slab_pre_alloc_hook+0x18/0x3b
        [<ffffffff810ef227>] kmem_cache_alloc_trace+0x25/0xba
        [<ffffffff812387e6>] T.492+0x24/0x26
        [<ffffffff81238816>] pci_get_subsys+0x2e/0x73
        [<ffffffff8123886c>] pci_get_device+0x11/0x13
        [<ffffffff814082a9>] usb_amd_find_chipset_info+0x3f/0x18a
      ...
      
      It turns out that this function calls pci_get_device under a spin_lock
      with irqs disabled, but the pci_get_device function is only allowed in
      preemptible context.
      
      This patch fixes the warning by making all data-structure
      modifications on temporal storage and commiting this back
      into the visible structure at the end. While at it, this
      patch also moves the pci_dev_put calls out of the spinlocks
      because this function might sleep too.
      Signed-off-by: NJoerg Roedel <joerg.roedel@amd.com>
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      9ab7927b
  16. 02 3月, 2011 1 次提交
    • A
      USB host: Move AMD PLL quirk to pci-quirks.c · ad93562b
      Andiry Xu 提交于
      This patch moves the AMD PLL quirk code in OHCI/EHCI driver to pci-quirks.c,
      and exports the functions to be used by xHCI driver later.
      
      AMD PLL quirk disable the optional PM feature inside specific
      SB700/SB800/Hudson-2/3 platforms under the following conditions:
      
      1. If an isochronous device is connected to OHCI/EHCI/xHCI port and is active;
      2. Optional PM feature that powers down the internal Bus PLL when the link is
         in low power state is enabled.
      
      Without AMD PLL quirk, USB isochronous stream may stutter or have breaks
      occasionally, which greatly impair the performance of audio/video streams.
      
      Currently AMD PLL quirk is implemented in OHCI and EHCI driver, and will be
      added to xHCI driver too. They are doing similar things actually, so move
      the quirk code to pci-quirks.c, which has several advantages:
      
      1. Remove duplicate defines and functions in OHCI/EHCI (and xHCI) driver and
         make them cleaner;
      2. AMD chipset information will be probed only once and then stored.
         Currently they're probed during every OHCI/EHCI initialization, move
         the detect code to pci-quirks.c saves the repeat detect cost;
      3. Build up synchronization among OHCI/EHCI/xHCI driver. In current
         code, every host controller enable/disable PLL only according to
         its own status, and may enable PLL while there is still isoc transfer on
         other HCs. Move the quirk to pci-quirks.c prevents this issue.
      Signed-off-by: NAndiry Xu <andiry.xu@amd.com>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Cc: Alex He <alex.he@amd.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      ad93562b
  17. 18 2月, 2011 1 次提交
  18. 05 2月, 2011 1 次提交
    • A
      USB host: Move AMD PLL quirk to pci-quirks.c · b7d5b439
      Andiry Xu 提交于
      This patch moves the AMD PLL quirk code in OHCI/EHCI driver to pci-quirks.c,
      and exports the functions to be used by xHCI driver later.
      
      AMD PLL quirk disable the optional PM feature inside specific
      SB700/SB800/Hudson-2/3 platforms under the following conditions:
      
      1. If an isochronous device is connected to OHCI/EHCI/xHCI port and is active;
      2. Optional PM feature that powers down the internal Bus PLL when the link is
         in low power state is enabled.
      
      Without AMD PLL quirk, USB isochronous stream may stutter or have breaks
      occasionally, which greatly impair the performance of audio/video streams.
      
      Currently AMD PLL quirk is implemented in OHCI and EHCI driver, and will be
      added to xHCI driver too. They are doing similar things actually, so move
      the quirk code to pci-quirks.c, which has several advantages:
      
      1. Remove duplicate defines and functions in OHCI/EHCI (and xHCI) driver and
         make them cleaner;
      2. AMD chipset information will be probed only once and then stored.
         Currently they're probed during every OHCI/EHCI initialization, move
         the detect code to pci-quirks.c saves the repeat detect cost;
      3. Build up synchronization among OHCI/EHCI/xHCI driver. In current
         code, every host controller enable/disable PLL only according to
         its own status, and may enable PLL while there is still isoc transfer on
         other HCs. Move the quirk to pci-quirks.c prevents this issue.
      Signed-off-by: NAndiry Xu <andiry.xu@amd.com>
      Cc: David Brownell <dbrownell@users.sourceforge.net>
      Cc: Alex He <alex.he@amd.com>
      Acked-by: NAlan Stern <stern@rowland.harvard.edu>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b7d5b439
  19. 23 10月, 2010 1 次提交
    • A
      OHCI: work around for nVidia shutdown problem · 3df7169e
      Alan Stern 提交于
      This patch (as1417) fixes a problem affecting some (or all) nVidia
      chipsets.  When the computer is shut down, the OHCI controllers
      continue to power the USB buses and evidently they drive a Reset
      signal out all their ports.  This prevents attached devices from going
      to low power.  Mouse LEDs stay on, for example, which is disconcerting
      for users and a drain on laptop batteries.
      
      The fix involves leaving each OHCI controller in the OPERATIONAL state
      during system shutdown rather than putting it in the RESET state.
      Although this nominally means the controller is running, in fact it's
      not doing very much since all the schedules are all disabled.  However
      there is ongoing DMA to the Host Controller Communications Area, so
      the patch also disables the bus-master capability of all PCI USB
      controllers after the shutdown routine runs.
      
      The fix is applied only to nVidia-based PCI OHCI controllers, so it
      shouldn't cause problems on systems using other hardware.  As an added
      safety measure, in case the kernel encounters one of these running
      controllers during boot, the patch changes quirk_usb_handoff_ohci()
      (which runs early on during PCI discovery) to reset the controller
      before anything bad can happen.
      Reported-by: NPali Rohár <pali.rohar@gmail.com>
      Signed-off-by: NAlan Stern <stern@rowland.harvard.edu>
      CC: David Brownell <david-b@pacbell.net>
      Tested-by: NPali Rohár <pali.rohar@gmail.com>
      CC: stable <stable@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      3df7169e
  20. 10 8月, 2010 1 次提交
  21. 12 10月, 2009 1 次提交
  22. 23 9月, 2009 1 次提交
    • D
      USB: Work around BIOS bugs by quiescing USB controllers earlier · db8be50c
      David Woodhouse 提交于
      We are seeing a number of crashes in SMM, when VT-d is enabled while
      'Legacy USB support' is enabled in various BIOSes.
      
      The BIOS is supposed to indicate which addresses it uses for DMA in a
      special ACPI table ("RMRR"), so that we can punch a hole for it when we
      set up the IOMMU.
      
      The problem is, as usual, that BIOS engineers are totally incompetent.
      They write code which will crash if the DMA goes AWOL, and then they
      either neglect to provide an RMRR table at all, or they put the wrong
      addresses in it. And of course they don't do _any_ QA, since that would
      take too much time away from their crack-smoking habit.
      
      The real fix, of course, is for consumers to refuse to buy motherboards
      which only have closed-source firmware available. If we had _open_
      firmware, bugs like this would be easy to fix.
      
      Since that's something I can only dream about, this patch implements an
      alternative -- ensuring that the USB controllers are handed off from the
      BIOS and quiesced _before_ the IOMMU is initialised. That would have
      been a much better design than this RMRR nonsense in the first place, of
      course. The bootloader has no business doing DMA after the OS has booted
      anyway.
      Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      db8be50c
  23. 20 8月, 2009 1 次提交
    • D
      USB: Work around BIOS bugs by quiescing USB controllers earlier · 13203227
      David Woodhouse 提交于
      We are seeing a number of crashes in SMM, when VT-d is enabled while
      'Legacy USB support' is enabled in various BIOSes.
      
      The BIOS is supposed to indicate which addresses it uses for DMA in a
      special ACPI table ("RMRR"), so that we can punch a hole for it when we
      set up the IOMMU.
      
      The problem is, as usual, that BIOS engineers are totally incompetent.
      They write code which will crash if the DMA goes AWOL, and then they
      either neglect to provide an RMRR table at all, or they put the wrong
      addresses in it. And of course they don't do _any_ QA, since that would
      take too much time away from their crack-smoking habit.
      
      The real fix, of course, is for consumers to refuse to buy motherboards
      which only have closed-source firmware available. If we had _open_
      firmware, bugs like this would be easy to fix.
      
      Since that's something I can only dream about, this patch implements an
      alternative -- ensuring that the USB controllers are handed off from the
      BIOS and quiesced _before_ the IOMMU is initialised. That would have
      been a much better design than this RMRR nonsense in the first place, of
      course. The bootloader has no business doing DMA after the OS has booted
      anyway.
      Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      13203227
  24. 16 6月, 2009 1 次提交
    • S
      USB: xhci: BIOS handoff and HW initialization. · 66d4eadd
      Sarah Sharp 提交于
      Add PCI initialization code to take control of the xHCI host controller
      away from the BIOS, halt, and reset the host controller.  The xHCI spec
      says that BIOSes must give up the host controller within 5 seconds.
      
      Add some host controller glue functions to handle hardware initialization
      and memory allocation for the host controller.  The current xHCI
      prototypes use PCI interrupts, but the xHCI spec requires MSI-X
      interrupts.  Add code to support MSI-X interrupts, but use the PCI
      interrupts for now.
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      66d4eadd
  25. 25 3月, 2009 1 次提交
  26. 08 1月, 2009 2 次提交
  27. 25 4月, 2008 1 次提交
  28. 02 2月, 2008 1 次提交
  29. 23 5月, 2007 1 次提交
  30. 13 7月, 2006 1 次提交
  31. 01 7月, 2006 1 次提交
  32. 15 4月, 2006 1 次提交
  33. 01 3月, 2006 1 次提交
  34. 14 2月, 2006 1 次提交
  35. 01 2月, 2006 1 次提交
    • D
      [PATCH] USB: fix EHCI early handoff issues · 401feafa
      David Brownell 提交于
      This moves the previously widely-used ehci-pci.c BIOS handoff
      code into the pci-quirks.c file, replacing the less widely used
      "early handoff" version that seems to cause problems lately.
      
      One notable change:  the "early handoff" version always enabled
      an SMI IRQ ... and did so even if the pre-Linux code said it was
      not using EHCI (and not expecting EHCI SMIs).  Looks like a goof
      in a workaround for some unknown BIOS version.
      
      This merged version only forcibly enables those IRQs when pre-Linux
      code says it's using EHCI.  And now it always forces them off "just
      in case".
      Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      401feafa
  36. 05 1月, 2006 1 次提交
  37. 05 11月, 2005 1 次提交