- 23 8月, 2017 2 次提交
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由 Jean-Louis Thekekara 提交于
This commit removes hard-coded '8' used for looping into struct nand_chip.id.data array. NAND_MAX_ID_LEN has been introduced by Artem Bityutskiy in 53552d22 for defining ids length in nand_flash_ids[] list. This commit unifies ids length in nand base driver. Signed-off-by: NJean-Louis Thekekara <jeanlouis.thekekara@parrot.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Boris Brezillon 提交于
The nand_scan_ident() function is not expected to allocate resources, and people are usually not calling nand_cleanup() if something fails between nand_scan_ident() and nand_scan_tail(). Move all functions that may allocate resource to the nand_scan_tail() path to prevent such resource leaks. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 03 8月, 2017 1 次提交
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由 Boris Brezillon 提交于
Commit 7d70f334 ("mtd: nand: add lock/unlock routines") introduced support for the Micron LOCK/UNLOCK commands but no one ever used the nand_lock/unlock() functions. Remove support for these vendor-specific operations from the core. If one ever wants to add them back they should be put in nand_micron.c and mtd->_lock/_unlock should be directly assigned from there instead of exporting the functions. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 08 7月, 2017 1 次提交
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由 Boris Brezillon 提交于
The code checks that ->_point is not NULL, but we should actually check ->_unpoint value which is dereferenced a few lines after the check. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 03 7月, 2017 1 次提交
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由 Dan Carpenter 提交于
We only want to hold the lock on the success path, not this error path. Fixes: 7ec4a37c ("mtd: nand: mediatek: add support for different MTK NAND FLASH Controller IP") Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 28 6月, 2017 3 次提交
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由 Cyrille Pitchen 提交于
The 35h instruction op code has two aliases/macro definitions: - SPINOR_OP_RDCR from include/linux/mtd/spi-nor.h - SPINOR_OP_RDSR2 from drivers/mtd/devices/serial_flash_cmds.h Actually, some manufacturers name the associated internal register Status Register 2 whereas other manufacturers name it Configuration Register hence the two different macros for the very same instruction op code. Since the spi-nor.h file is the reference file for all SPI NOR instruction op codes, this patch removes the definition of the SPINOR_OP_RDSR2 macro. Also the SPINOR_OP_RDSR2 macro will be associated to another instruction op code in a further patch so we need to avoid a conflict defining this macro twice. Indeed the JESD216 rev B specification, defining the SFDP tables, also refers to the 3Eh and 3Fh instruction op codes to write/read the Status Register 2 on some SPI NOR flash memories, the 35h op code still being used to read the Configuration Register/Status Register 2 on other memories. Signed-off-by: NCyrille Pitchen <cyrille.pitchen@microchip.com> Acked-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Arnd Bergmann 提交于
The variable was already marked 'const' before the previous patch, but the qualifier was in an unusual place, and now the extra 'const' causes a harmless warning: drivers/mtd/spi-nor/cadence-quadspi.c:1286:34: error: duplicate 'const' declaration specifier [-Werror=duplicate-decl-specifier] This removes the other 'const' instead. Fixes: f993c123 ("mtd: spi-nor: cqspi: make of_device_ids const") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Christoph Hellwig 提交于
Instead move it to the callers. Those that either don't use bio_data() or page_address() or are specific to architectures that do not support highmem are skipped. Signed-off-by: NChristoph Hellwig <hch@lst.de> Signed-off-by: NJens Axboe <axboe@kernel.dk>
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- 27 6月, 2017 2 次提交
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由 Harry Chou 提交于
It's an 8 MiB flash with 4 KiB erase sectors. Signed-off-by: NHarry Chou <HarryYC.Chou@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Alexander Sverdlin 提交于
This chip supports stateless 4-byte opcodes, dual and quad read and uniform 4K-byte erase. Signed-off-by: NAlexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 25 6月, 2017 5 次提交
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由 Xiaolei Li 提交于
Currently, we use the fixed ACC timing 0x10804211. This is not the best setting for each case. Actually, MTK NAND controller can adapt ACC timings dynamically according to nfi clock frequence. Implement the ->setup_data_interface() hook to optimize driver performance. Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Xiaolei Li 提交于
There is no need to add mtk_ecc_hw_init during ecc resume, because there always takes mtk_ecc_wait_idle in the function mtk_ecc_enable. Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Xiaolei Li 提交于
chip->select_chip will do nfc runtime configuration. There is no need to do mtk_nfc_hw_init before it. Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Xiaolei Li 提交于
Currently, ecc encode irq is enabled when writing page with hwecc, but we actually do not wait for this irq done. Because NFI and ECC work in parallel, nfi irq and ecc irq almost come together. Now, there are two steps to check whether page data are totally written. First, wait for nfi irq INTR_AHB_DONE. This is to ensure all data in RAM are received by NFI. Second, polling the register NFI_ADDRCNTR till all data include ecc parity data runtime generated by ECC are sent to NAND device. So, it is redunant to enable ecc irq without waiting for it. Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Xiaolei Li 提交于
Currently, we trigger ECC HW before setting ecc irq. It is incorrect. Because ECC starts working once the register ECC_CTL_REG is set as ECC_OP_ENABLE. And this may lead an abnormal behavior of ecc irq. So, should enable ecc irq at first, then trigger ECC. Fixes: 1d6b1e46 ("mtd: mediatek: driver for MTK Smart Device") Signed-off-by: NXiaolei Li <xiaolei.li@mediatek.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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- 24 6月, 2017 2 次提交
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由 Brian Norris 提交于
Some recent patches caused churn around this area, and checkpatch noticed the existing issues. Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
This fixes following warning: include/linux/kern_levels.h:4:18: warning: format '%X' expects argument of type 'unsigned int', but argument 2 has type 'size_t {aka long unsigned int}' [-Wformat=] Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 23 6月, 2017 6 次提交
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由 Rafał Miłecki 提交于
This makes TRX parsing code reusable with other platforms and parsers. Please note this patch doesn't really change anything in the existing code, just moves it. There is still some place for improvement (e.g. working on non-hacky method of checking rootfs format) but it's not really a subject of this change. Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
Some devices have partitions that are kind of containers with extra subpartitions / volumes instead of e.g. a simple filesystem data. To support such cases we need to first create normal flash device partitions and then take care of these special ones. It's very common case for home routers. Depending on the vendor there are formats like TRX, Seama, TP-Link, WRGG & more. All of them are used to embed few partitions into a single one / single firmware file. Ideally all vendors would use some well documented / standardized format like UBI (and some probably start doing so), but there are still countless devices on the market using these poor vendor specific formats. This patch extends MTD subsystem by allowing to specify list of parsers that should be tried for a given partition. Supporting such poor formats is highly unlikely to be the top priority so these changes try to minimize maintenance cost to the minimum. It reuses existing code for these new parsers and just adds a one property and one new function. This implementation requires setting partition parsers in a flash parser. A proper change of bcm47xxpart will follow and in the future we will hopefully also find a solution for doing it with ofpart ("fixed-partitions"). Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
Some flash device partitions can be containers with extra subpartitions (volumes). All callbacks are already capable of this additional level of indirection. This patch makes sure we always display subpartitions using a tree structure and takes care of deleting subpartitions when parent gets removed. Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
This prepares mtd subsystem for the new feature: subpartitions. In some cases flash device partition can be a container with extra subpartitions (volumes). So far there was a flat structure implemented. One master (flash device) could be partitioned into few partitions. Every partition got its master and it was enough to get things running. To support subpartitions we need to store pointer to the parent for each partition. This is required to implement more natural tree structure and handle all recursion and offsets calculation. To make code consistent this patch renamed "master" to the "parent" in places where we can be dealing with subpartitions. Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
When support for sysfs "offset" file was added it missed to update the del_mtd_partitions function. It deletes partitions just like mtd_del_partition does so both should also take care of removing sysfs files. This change moves sysfs_remove_files call to the shared function to fix this issue. Fixes: a62c24d7 ("mtd: part: Add sysfs variable for offset of partition") Cc: Dan Ehrenberg <dehrenberg@chromium.org> Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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由 Rafał Miłecki 提交于
There are two similar functions handling deletion. One handles single partition and another the whole MTD flash device. They share (duplicate) some code so it makes sense to add a small helper for that part. Function del_mtd_partitions has been moved a bit to keep all deleting stuff together. Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
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- 22 6月, 2017 1 次提交
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由 Cédric Le Goater 提交于
The segment registers of the SMC controller provide a way to configure the mapping windows of the chips on the AHB bus. The settings are required to be correct when the controller operates in Command mode, which is the case for DMAs and the LPC mapping. This tries to set the segment registers of each chip depending on the size of the flash device and depending on the previous segment settings, in order to have a contiguous window across multiple chips. Unfortunately, the AST2500 SPI controller has a bug and it is not possible to configure a full 128MB window for a chip of the same size. The window size needs to be restricted to 120MB. This issue only applies to CE0. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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- 21 6月, 2017 6 次提交
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由 Cédric Le Goater 提交于
There is no need to keep the dummy bytes in the control register if the command mode is not kept also. This could lead to an inconsistent setting : normal read mode (command 0x3) and dummy bytes. It is to be noted that the HW allows such a configuration. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Cédric Le Goater 提交于
These devices are used on OpenPOWER systems. The SPI_NOR_DUAL_READ flags is added for the Aspeed SoCs which do not support QUAD reads. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Cédric Le Goater 提交于
These modules are used on the OpenPOWER Witherspoon systems to hold the POWER9 host firmware image. The SPI_NOR_DUAL_READ flags is added for the Aspeed SoCs which do not support QUAD reads. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Arvind Yadav 提交于
of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com> Reviewed-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Benjamin Herrenschmidt 提交于
Similar to the other ones, different size. The "JV" suffix is in the datasheet, I haven't seen mentions of a different one. The datasheet indicates DUAL and QUAD are supported. http://www.winbond.com/resource-files/w25m512jv%20revc%2001062017.pdfSigned-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NJoel Stanley <joel@jms.id.au> Signed-off-by: NCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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由 Brian Norris 提交于
This code is going to be reused for parsers matched using OF so let's factor it out to make this easier. Signed-off-by: NBrian Norris <computersforpeace@gmail.com> Signed-off-by: NRafał Miłecki <rafal@milecki.pl> Acked-by: NBrian Norris <computersforpeace@gmail.com>
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- 20 6月, 2017 10 次提交
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由 Prabhakar Kushwaha 提交于
All IFC version >= 1.0 use 28nm technology for SRAM. Here SRAM has a requirement to initialize before any read operation performed for avoiding ECC Error. So update condition check to initialize SRAM for all IFC version >= 1.0.0 Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
Introduce some macros and helpers to avoid magic numbers and rename macros/functions for clarification. - We see '| 2' in several places. This means Data Cycle in MAP11 mode. The Denali User's Guide says bit[1:0] of MAP11 is like follows: b'00 = Command Cycle b'01 = Address Cycle b'10 = Data Cycle So, this commit added DENALI_MAP11_{CMD,ADDR,DATA} macros. - We see 'denali->flash_mem + 0x10' in several places, but 0x10 is a magic number. Actually, this accesses the data port of the Host Data/Command Interface. So, this commit added DENALI_HOST_DATA. On the other hand, 'denali->flash_mem' gets access to the address port, so DENALI_HOST_ADDR was also added. - We see 'index_addr(denali, cmd, 0x1)' in denali_erase(), but 0x1 is a magic number. 0x1 means the erase operation. Replace 0x1 with DENALI_ERASE. - Rename index_addr() to denali_host_write() for clarification - Denali User's Guide says MAP{00,01,10,11} for access mode. Match the macros with terminology in the IP document. - Rename struct members as follows: flash_bank -> active_bank (currently selected bank) flash_reg -> reg (base address of registers) flash_mem -> host (base address of host interface) devnum -> devs_per_cs (devices connected in parallel) bbtskipbytes -> oob_skip_bytes (number of bytes to skip in OOB) Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
Now this driver is ready to remove NAND_SKIP_BBTSCAN. The BBT descriptors in denali.c are equivalent to the ones in nand_bbt.c. There is no need to duplicate the equivalent structures. The with-oob decriptors do not work for this driver anyway. The bbt_pattern (offs = 8) and the version (veroffs = 12) area overlaps the ECC area. Set NAND_BBT_NO_OOB flag to use the no_oob variant of the BBT descriptors. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
As Russell and Lars stated in the discussion [1], using devm_k*alloc() with DMA is not a good idea. Let's use kmalloc (not kzalloc because no need for zero-out). Also, allocate the buffer as late as possible because it must be freed for any error that follows. [1] https://lkml.org/lkml/2017/3/8/693Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Lars-Peter Clausen <lars@metafoo.de> Acked-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
For ecc->read_page() and ecc->write_page(), it is possible to call dma_map_single() against the given buffer. This bypasses the driver internal bounce buffer and save the memcpy(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
Recent versions of this IP support automatic erased page detection. If an erased page is detected on reads, the controller does not set INTR__ECC_UNCOR_ERR, but INTR__ERASED_PAGE. The detection of erased pages is based on the number of zeros in a page; if the number of zeros is less than the value in the field ERASED_THRESHOLD, the page is assumed as erased. Please note ERASED_THRESHOLD specifies the number of zeros in a _page_ instead of an ECC chunk. Moreover, the controller does not provide a way to know the actual number of bitflips. Actually, an erased page (all 0xff) is not an ECC correctable pattern on the Denali ECC engine. In other words, there may be overlap between the following two: [1] a bit pattern reachable from a valid payload + ECC pattern within ecc.strength bitflips [2] a bit pattern reachable from an erased state (all 0xff) within ecc.strength bitflips So, this feature may intercept ECC correctable patterns, then replace [1] with [2]. After all, this feature can work safely only when ECC_THRESHOLD == 1, i.e. detect erased pages without any bitflips. This should be the case most of the time. If there is a bitflip or more, the driver will fallback to the software method by using nand_check_erased_ecc_chunk(). Strangely enough, the driver still has to fill the buffer with 0xff in case of INTR__ERASED_PAGE because the ECC correction engine has already manipulated the data in the buffer before it judges erased pages. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
The Denali IP adopts the syndrome page layout; payload and ECC are interleaved, with BBM area always placed at the beginning of OOB. The figure below shows the page organization for ecc->steps == 2: |----------------| |-----------| | | | | | | | | | Payload0 | | | | | | | | | | | | | | | |----------------| | in-band | | ECC0 | | area | |----------------| | | | | | | | | | | | Payload1 | | | | | | | | | | | |----------------| |-----------| | BBM | | | |----------------| | | |Payload1 (cont.)| | | |----------------| |out-of-band| | ECC1 | | area | |----------------| | | | OOB free | | | |----------------| |-----------| The current raw / oob accessors do not take that into consideration, so in-band and out-of-band data are transferred as stored in the device. In the case above, in-band: Payload0 + ECC0 + Payload1(partial) out-of-band: BBM + Payload1(cont.) + ECC1 + OOB-free This is wrong. As the comment block of struct nand_ecc_ctrl says, driver callbacks must hide the specific layout used by the hardware and always return contiguous in-band and out-of-band data. The current implementation is completely screwed-up, so read/write callbacks must be re-worked. Also, it is reasonable to support PIO transfer in case DMA may not work for some reasons. Actually, the Data DMA may not be equipped depending on the configuration of the RTL. This can be checked by reading the bit 4 of the FEATURES register. Even if the controller has the DMA support, dma_set_mask() and dma_map_single() could fail. In either case, the driver can fall back to the PIO transfer. Slower access would be better than giving up. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
It is not a good idea to re-use macros that represent a specific register bit field for the transfer direction. It is true that bit 8 indicates the direction for the MAP10 pipeline operation and the data DMA operation, but this is not valid across the IP. Use a simple flag (write: 1, read: 0) for the direction. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
Now struct nand_buf has only two members, so I see no reason for the separation. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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由 Masahiro Yamada 提交于
This driver stores the currently addressed page into denali->page, which is later read out by helper functions. While I am tackling on this driver, I often missed to insert "denali->page = page;" where needed. This makes page_read/write callbacks to get access to a wrong page, which is a bug hard to figure out. Instead, I'd rather pass the page via function argument because the compiler's prototype checks will help to detect bugs. For the same reason, propagate dma_addr to the DMA helpers instead of denali->buf.dma_buf . Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
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