1. 09 4月, 2017 13 次提交
  2. 07 3月, 2017 1 次提交
    • M
      arm64: KVM: Survive unknown traps from guests · ba4dd156
      Mark Rutland 提交于
      Currently we BUG() if we see an ESR_EL2.EC value we don't recognise. As
      configurable disables/enables are added to the architecture (controlled
      by RES1/RES0 bits respectively), with associated synchronous exceptions,
      it may be possible for a guest to trigger exceptions with classes that
      we don't recognise.
      
      While we can't service these exceptions in a manner useful to the guest,
      we can avoid bringing down the host. Per ARM DDI 0487A.k_iss10775, page
      D7-1937, EC values within the range 0x00 - 0x2c are reserved for future
      use with synchronous exceptions, and EC values within the range 0x2d -
      0x3f may be used for either synchronous or asynchronous exceptions.
      
      The patch makes KVM handle any unknown EC by injecting an UNDEFINED
      exception into the guest, with a corresponding (ratelimited) warning in
      the host dmesg. We could later improve on this with with a new (opt-in)
      exit to the host userspace.
      
      Cc: Dave Martin <dave.martin@arm.com>
      Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      ba4dd156
  3. 06 3月, 2017 1 次提交
  4. 08 2月, 2017 3 次提交
  5. 03 2月, 2017 1 次提交
    • W
      arm64: KVM: Save/restore the host SPE state when entering/leaving a VM · f85279b4
      Will Deacon 提交于
      The SPE buffer is virtually addressed, using the page tables of the CPU
      MMU. Unusually, this means that the EL0/1 page table may be live whilst
      we're executing at EL2 on non-VHE configurations. When VHE is in use,
      we can use the same property to profile the guest behind its back.
      
      This patch adds the relevant disabling and flushing code to KVM so that
      the host can make use of SPE without corrupting guest memory, and any
      attempts by a guest to use SPE will result in a trap.
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: Alex Bennée <alex.bennee@linaro.org>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      f85279b4
  6. 30 1月, 2017 2 次提交
  7. 27 1月, 2017 1 次提交
  8. 25 1月, 2017 1 次提交
  9. 25 12月, 2016 1 次提交
  10. 09 12月, 2016 1 次提交
    • M
      arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest · 21cbe3cc
      Marc Zyngier 提交于
      The ARMv8 architecture allows the cycle counter to be configured
      by setting PMSELR_EL0.SEL==0x1f and then accessing PMXEVTYPER_EL0,
      hence accessing PMCCFILTR_EL0. But it disallows the use of
      PMSELR_EL0.SEL==0x1f to access the cycle counter itself through
      PMXEVCNTR_EL0.
      
      Linux itself doesn't violate this rule, but we may end up with
      PMSELR_EL0.SEL being set to 0x1f when we enter a guest. If that
      guest accesses PMXEVCNTR_EL0, the access may UNDEF at EL1,
      despite the guest not having done anything wrong.
      
      In order to avoid this unfortunate course of events (haha!), let's
      sanitize PMSELR_EL0 on guest entry. This ensures that the guest
      won't explode unexpectedly.
      
      Cc: stable@vger.kernel.org #4.6+
      Acked-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      21cbe3cc
  11. 18 11月, 2016 1 次提交
  12. 17 11月, 2016 1 次提交
    • S
      arm64: Support systems without FP/ASIMD · 82e0191a
      Suzuki K Poulose 提交于
      The arm64 kernel assumes that FP/ASIMD units are always present
      and accesses the FP/ASIMD specific registers unconditionally. This
      could cause problems when they are absent. This patch adds the
      support for kernel handling systems without FP/ASIMD by skipping the
      register access within the kernel. For kvm, we trap the accesses
      to FP/ASIMD and inject an undefined instruction exception to the VM.
      
      The callers of the exported kernel_neon_begin_partial() should
      make sure that the FP/ASIMD is supported.
      
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
      Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
      Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
      [catalin.marinas@arm.com: add comment on the ARM64_HAS_NO_FPSIMD conflict and the new location]
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      82e0191a
  13. 14 11月, 2016 1 次提交
  14. 05 11月, 2016 1 次提交
    • M
      arm/arm64: KVM: Perform local TLB invalidation when multiplexing vcpus on a single CPU · 94d0e598
      Marc Zyngier 提交于
      Architecturally, TLBs are private to the (physical) CPU they're
      associated with. But when multiple vcpus from the same VM are
      being multiplexed on the same CPU, the TLBs are not private
      to the vcpus (and are actually shared across the VMID).
      
      Let's consider the following scenario:
      
      - vcpu-0 maps PA to VA
      - vcpu-1 maps PA' to VA
      
      If run on the same physical CPU, vcpu-1 can hit TLB entries generated
      by vcpu-0 accesses, and access the wrong physical page.
      
      The solution to this is to keep a per-VM map of which vcpu ran last
      on each given physical CPU, and invalidate local TLBs when switching
      to a different vcpu from the same VM.
      Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      94d0e598
  15. 22 9月, 2016 5 次提交
  16. 12 9月, 2016 1 次提交
  17. 09 9月, 2016 1 次提交
    • M
      arm64/kvm: use {read,write}_sysreg() · 1f3d8699
      Mark Rutland 提交于
      A while back we added {read,write}_sysreg accessors to handle accesses
      to system registers, without the usual boilerplate asm volatile,
      temporary variable, etc.
      
      This patch makes use of these in the arm64 KVM code to make the code
      shorter and clearer.
      
      At the same time, a comment style violation next to a system register
      access is fixed up in reset_pmcr, and comments describing whether
      operations are reads or writes are removed as this is now painfully
      obvious.
      
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Will Deacon <will.deacon@arm.com>
      Acked-by: NChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: NMark Rutland <mark.rutland@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      1f3d8699
  18. 08 9月, 2016 4 次提交