1. 29 3月, 2017 11 次提交
    • B
      soc: qcom: smd: Transition client drivers from smd to rpmsg · 5052de8d
      Bjorn Andersson 提交于
      By moving these client drivers to use RPMSG instead of the direct SMD
      API we can reuse them ontop of the newly added GLINK wire-protocol
      support found in the 820 and 835 Qualcomm platforms.
      
      As the new (RPMSG-based) and old SMD implementations are mutually
      exclusive we have to change all client drivers in one commit, to make
      sure we have a working system before and after this transition.
      Acked-by: NAndy Gross <andy.gross@linaro.org>
      Acked-by: NKalle Valo <kvalo@codeaurora.org>
      Acked-by: NMarcel Holtmann <marcel@holtmann.org>
      Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5052de8d
    • R
      vxlan: don't age NTF_EXT_LEARNED fdb entries · def499c9
      Roopa Prabhu 提交于
      vxlan driver already implicitly supports installing
      of external fdb entries with NTF_EXT_LEARNED. This
      patch just makes sure these entries are not aged
      by the vxlan driver. An external entity managing these
      entries will age them out. This is consistent with
      the use of NTF_EXT_LEARNED in the bridge driver.
      Signed-off-by: NRoopa Prabhu <roopa@cumulusnetworks.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      def499c9
    • D
      Merge branch 'net-dpipe' · 2a69ca71
      David S. Miller 提交于
      Jiri Pirko says:
      
      ====================
      Add support for pipeline debug (dpipe)
      
      Arkadi says:
      
      While doing the hardware offloading process much of the hardware
      specifics cannot be presented. An example for such is the routing
      LPM algorithm which differ in hardware implementation from the
      kernel software implementation. The only information the user receives
      is whether specific route is offloaded or not, but he cannot really
      understand the underlying implementation nor get the specific statistics
      related to that process.
      
      Another example is ACL offload using TC which is commonly implemented
      using TCAM memory. Currently there is no capability to gain visibility
      into the TCAM structure and to debug suboptimal resource allocation.
      
      This patchset introduces capability for exporting the ASICs pipeline
      abstraction via devlink infrastructure, which should serve as an
      complementary tool. This infrastructure allows the user to get visibility
      into the ASIC by modeling it as a set of match/action tables.
      
      The main objects defined:
      Table - abstraction for a single pipeline stage. Contains the
              available match/actions and counter availability.
      Entry - entry in a specific table with specific matches/actions
              values and dedicated counter.
      Header/field - tuples which describes the tables behavior.
      
      As an example one of the ASIC's L3 blocks will be modeled. The egress
      rif (router interface) table is the final step in the L3 pipeline
      processing which does match on the internal rif index which was
      determined before by the routing logic. The erif table determines
      whether to forward or drop the packet and updates the corresponding
      rif L3 statistics.
      
      To expose this internal resources a special metadata header will
      be introduced that describes the internal information gathered by
      the ASIC's pipeline and contains the following fields: rif_port_index,
      forward and drop.
      
      Some internal hardware resources have direct mapping to kernel
      objects. For example the rif_port_index is mapped to the net-devices
      ifindex. By providing this mapping the users gains visibility into
      the offloading process.
      
      Follow-up work will include exporting more L3 tables which will give
      visibility into the routing process.
      
      First stage is adding support for dpipe in devlink. Next add support
      in spectrum driver. Finally implement egress router interface
      (erif) table for spectrum ASIC as an example.
      
      ---
      v1->v2: Please see individual patches
      ====================
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2a69ca71
    • A
      mlxsw: spectrum: Add Support for erif table entries access · 2ba5999f
      Arkadi Sharshevsky 提交于
      Implement dpipe's table ops for erif table which provide:
      1. Getting the entries in the table with the associate values.
      	- match on "mlxsw_meta:erif_index"
      	- action on "mlxsw_meta:forwared_out"
      2. Synchronize the hardware in case of enabling/disabling counters which
         mean removing erif counters from all interfaces.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2ba5999f
    • A
      mlxsw: spectrum_router: Add rif helper functions · fd1b9d41
      Arkadi Sharshevsky 提交于
      Add rif helper function to access the rif index and rif devices ifindex.
      This functions will be used by dpipe in order to dump the rif table.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fd1b9d41
    • A
      mlxsw: spectrum: Support for counters on router interfaces · e0c0afd8
      Arkadi Sharshevsky 提交于
      Add support for counter allocation on router interfaces. The allocation
      depends on the counter state of relevant table. In case the counting is
      disabled or no counters left the counter index will be set as invalid.
      
      Also a counter pool for router allocation is added.
      Signed-off-by: NArakdi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e0c0afd8
    • A
      mlxsw: reg: Add Router Interface Counter Register · ba73e97a
      Arkadi Sharshevsky 提交于
      The RICNT register retrieves per port performance counter. It will be
      used to query the router interfaces statistics.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ba73e97a
    • A
      mlxsw: spectrum: Add definition for egress rif table · d54b70fe
      Arkadi Sharshevsky 提交于
      Add definition for egress router interface table. This table describes
      the final part in the routing pipeline. This table matches the egress
      interface index (rif index, which is set by the previous stages and
      determine the out port) and makes the decision of forwarding the packet
      towards the L2 logic or dropping it.
      
      The metadata header is added to represent this internal information.
      The rif index field is mapped logically to netdevice ifindex.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d54b70fe
    • A
      mlxsw: spectrum: Add placeholder for dpipe · 230ead01
      Arkadi Sharshevsky 提交于
      Add placeholder for dpipe. Support for specific tables and headers will
      be introduced in following patches. The headers are shared between all
      mlxsw_sp instances.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      230ead01
    • A
      mlxsw: reg: Add counter fields to RITR register · 0f630fcb
      Arkadi Sharshevsky 提交于
      Update RITR for counter support. This allows adding counters for
      ASIC's router ports.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0f630fcb
    • A
      devlink: Support for pipeline debug (dpipe) · 1555d204
      Arkadi Sharshevsky 提交于
      The pipeline debug is used to export the pipeline abstractions for the
      main objects - tables, headers and entries. The only support for set is
      for changing the counter parameter on specific table.
      
      The basic structures:
      
      Header - can represent a real protocol header information or internal
               metadata. Generic protocol headers like IPv4 can be shared
               between drivers. Each driver can add local headers.
      
      Field - part of a header. Can represent protocol field or specific ASIC
              metadata field. Hardware special metadata fields can be mapped
              to different resources, for example switch ASIC ports can have
              internal number which from the systems point of view is mapped
              to netdeivce ifindex.
      
      Match - represent specific match rule. Can describe match on specific
              field or header. The header index should be specified as well
              in order to support several header instances of the same type
              (tunneling).
      
      Action - represents specific action rule. Actions can describe operations
               on specific field values for example like set, increment, etc.
               And header operation like add and delete.
      
      Value - represents value which can be associated with specific match or
              action.
      
      Table - represents a hardware block which can be described with match/
              action behavior. The match/action can be done on the packets
              data or on the internal metadata that it gathered along the
              packets traversal throw the pipeline which is vendor specific
              and should be exported in order to provide understanding of
              ASICs behavior.
      
      Entry - represents single record in a specific table. The entry is
              identified by specific combination of values for match/action.
      
      Prior to accessing the tables/entries the drivers provide the header/
      field data base which is used by driver to user-space. The data base
      is split between the shared headers and unique headers.
      Signed-off-by: NArkadi Sharshevsky <arkadis@mellanox.com>
      Signed-off-by: NJiri Pirko <jiri@mellanox.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1555d204
  2. 28 3月, 2017 28 次提交
  3. 27 3月, 2017 1 次提交
    • S
      net/mlx5e: Fail safe mtu and lro setting · 2e20a151
      Saeed Mahameed 提交于
      Use the new fail-safe channels switch mechanism to set new
      netdev mtu and lro settings.
      
      MTU and lro settings demand some HW configuration changes after new
      channels are created and ready for action. In order to unify switch
      channels routine for LRO and MTU changes, and maybe future configuration
      features, we now pass to it a modify HW function pointer to be
      invoked directly after old channels are de-activated and before new
      channels are activated.
      Signed-off-by: NSaeed Mahameed <saeedm@mellanox.com>
      Reviewed-by: NTariq Toukan <tariqt@mellanox.com>
      2e20a151